AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 32

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9869
Because the CPGA processes signals in the continuous time
domain, its performance vs. bias setting remains mostly
independent of the sample rate. Table 25 shows how the typical
current consumption seen at AVDD varies as a function of
Register 0x13, Bits[7:5], while the remaining bits are maintained at
their default settings of 0. Only four of the possible settings result
in any reduction in current consumption relative to the default
setting. Reducing the bias level typically results in degradation
in the THD vs. frequency performance as shown in Figure 35.
This is due to a reduction of the amplifier’s unity gain bandwidth,
while the SNR performance remains relatively unaffected.
Table 25. Analog Supply Current vs. CPGA Bias Settings at
f
Bit 7
0
0
0
0
1
1
1
1
with RxPGA = 0 and +36 dB, AIN = −1 dBFS, LPF set to 26 MHz, f
ADC
Figure 35. THD vs. f
= 65 MSPS
65.0
62.5
60.0
57.5
55.0
52.5
50.0
47.5
45.0
42.5
40.0
000
Bit 6
0
0
1
1
0
0
1
1
IN
Performance and CPGA Bias Settings (000, 001, 010, 100
001
CPGA BIAS SETTING-BITS (7:5)
SNR_RxPGA = 0dB
SNR_RxPGA = 36dB
THD_RxPGA = 0dB
THD_RxPGA = 36dB
010
Bit 5
0
1
0
1
0
1
0
1
011
∆mA
0
−27
−42
−51
−55
+27
+69
+27
ADC
= 50 MSPS)
100
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
Rev. 0 | Page 32 of 36
The SPGA is implemented as a switched capacitor amplifier,
therefore, its performance vs. bias level is mostly dependent on
the sample rate. Figure 36 shows how the typical current consump-
tion seen at AVDD varies as a function of Register 0x13, Bits[4:3]
and sample rate, while the remaining bits are maintained at the
default setting of 0. Figure 37 shows how the SNR and THD
performance is affected for a 10 MHz sine wave input as the
ADC sample rate is swept from 20 MHz to 80 MHz. The SNR
and THD performance remains relatively stable, suggesting that
the SPGA bias can often be reduced from its default setting
without impacting the device’s overall performance.
Figure 37. SNR and THD Performance vs. f
Figure 36. AVDD Current vs. SPGA Bias Setting and Sample Rate
61
60
59
58
57
56
55
54
53
52
51
RxPGA = 0 dB, f
210
205
200
195
190
185
180
175
170
20
20
30
30
IN
= 10 MHz, LPF set to 26 MHz, AIN = −1 dBFS
40
ADC SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
40
01
00
10
11
THD-00
THD-01
THD-10
THD-11
50
50
ADC
60
and SPGA Bias Setting with
60
70
SNR-00
SNR-01
SNR-10
SNR-11
70
80
–54
–56
–58
–60
–62
–64
–66
–68
–70
–72
–74
80