AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 20

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9869
TxPGA CONTROL
The AD9869 also contains a digital PGA in the Tx path distri-
buted between the TxDAC and IAMP. The TxPGA is used to
control the peak current from the TxDAC and IAMP over a
7.5 dB and 19.5 dB span, respectively, with 0.5 dB resolution.
A 6-bit word is used to set the TxPGA attenuation according to
the mapping shown in Figure 17. The TxDAC gain mapping is
applicable only when Bit 0 of Register 0x0E is set, and only
when the 4 LSBs of the 6-bit gain word are relevant.
–10
–11
–12
–13
–14
–15
–16
–17
–18
–19
–20
–1
–2
–3
–4
–5
–6
–7
–8
–9
0
0
Figure 17. Digital Gain Mapping of TxPGA
8
6-BIT DIGITAL CODE (Decimal Equivalent)
IAMPs IOUTN OUTPUT
HAS 19.5dB RANGE
16
24
32
TxDACs IOUTP OUTPUT
HAS 7.5dB RANGE
40
48
56
64
Rev. 0 | Page 20 of 36
The TxPGA register can be updated via the PGA[5:0] port or
SPI port. The first method should be considered for fast updates
of the TxPGA register. Its operation is similar to the description
in the RxPGA Control section. The SPI port allows direct
update and readback of the TxPGA register via Register 0x0A
with an update rate limited to 1.6 MSPS (SCLK = 32 MHz).
Bit 6 of Register 0x0A must be set for a read or write operation.
Table 16 lists the SPI registers pertaining to the TxPGA. The
TxPGA control register default setting is for minimum attenua-
tion (0 dBFS) with the PGA[5:0] port disabled for Tx gain control.
Table 16. SPI Registers TxPGA Control
Address (Hex)
0x0A
0x0B
0x0E
Bit
6
5:0
6
5
0
Description
Enable TxPGA update via SPI.
TxPGA gain code.
Select TxPGA via PGA[5:0].
Select RxPGA via PGA[5:0].
TxDAC output (IAMP disabled).