AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 18

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9869
The Rx[5:0] port operates in the following manner with the SPI
register default settings:
1.
2.
3.
RXSYNC
To add flexibility to the full-duplex digital interface port, several
programming options are available in the SPI registers. These
options are listed in Table 14. The timing for the Tx[5:0] and/or
Rx[5:0] ports can be independently changed by selecting either
the rising or falling clock edge as the sampling/validating edge
of the clock. Inverting RXCLK (via Bit 1 of Register 0x05) affects
both the Rx and Tx interface because they both use RXCLK.
Table 14. SPI Registers for Full-Duplex Interface
Address (Hex)
0x05
0x0B
0x0C
0x0D
0x0E
RXCLK
Rx[5:0]
Two consecutive nibbles of the Rx data are multiplexed
together to form a 12-bit data-word in twos complement
format.
The Rx data is valid on the rising edge of RXCLK, as
illustrated in the timing diagram shown in Figure 13.
The RXSYNC signal is used to indicate which word belongs
to which nibble. While RXSYNC is low, the first nibble of
every word is transmitted as the most significant nibble.
The second nibble of that same word is transmitted on the
following RXSYNC high level as the least significant nibble.
Rx0LSB
Figure 13. Full-Duplex Rx Port Timing
Rx1MSB
Bit
2
1
0
2
4
3
2
1
0
5
4
3
2
1
0
7
t
DV
Rx1LSB
Description
OSCIN to RXCLK.
Invert RXCLK.
Disable RXCLK.
Rx gain on Tx port.
Invert TXSYNC.
Tx 5/5 nibble.
LS nibble first.
TXCLK negative edge.
Twos complement.
Rx port three-state.
Invert RXSYNC.
Rx 5/5 nibble.
LS nibble first.
RXCLK negative edge.
Twos complement.
Low digital drive strength.
t
DH
Rx2MSB
Rx3LSB
Rx3MSB
Rev. 0 | Page 18 of 36
The default Tx and Rx data input formats are twos complement,
but can be changed to straight binary. The default TXSYNC and
RXSYNC settings can be changed such that the first nibble of the
word appears while either TXSYNC, RXSYNC, or both are high.
In addition, the least significant nibble can be selected as the
first nibble of the word (least significant nibble first). The
output driver strength can also be reduced for lower data rate
applications.
For the AD9869, the most significant nibble defaults to 6 bits,
and the least significant nibble defaults to 4 bits. This can be
changed so that the least significant nibble and most significant
nibble have 5 bits each. To accomplish this, set the 5/5 nibble bit
(Bit 3 in Register 0x0C and Bit 3 in Register 0x0D), and use the
Tx[5:1] and Rx[5:1] data pins.
Figure 14 shows a possible digital interface between an ASIC
and the AD9869. The AD9869 serves as the master generating
the required clocks for the ASIC. This interface requires that the
ASIC reserve 16 pins for the interface, assuming a 6-bit nibble
width and the use of the Tx port for RxPGA gain control. Note
that the ASIC pin allocation can be reduced by 3 if a 5-bit nibble
width is used and the gain (or gain strobe) of the RxPGA is
controlled via the SPI port.
DIGITAL ASIC
Rx DATA[5:0]
Tx DATA[5:0]
RX_SYNC
TX_SYNC
Figure 14. Example of a Full-Duplex Digital Interface
CLKIN
with Optional RxPGA Gain Control via Tx[5:0]
OPTIONAL
FROM
CRYSTAL
OR MASTER CLK
Tx[5:0]
GAIN
RXSYNC
TXSYNC
RXCLK
CLKOUT1
CLKOUT2
OSCIN
Rx[5:0]
AD9868/AD9869
10/12
10/12
6
TO
RxPGA
TO
Tx DIGITAL
FILTER
FROM
RxADC