AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 30

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9869
POWER CONTROL AND DISSIPATION
POWER-DOWN
The AD9869 provides the ability to control the power-on state
of various functional blocks. The state of the PWRDWN pin,
along with the contents of Register 0x01 and Register 0x02,
allow two user-defined power settings that are pin-selectable.
The default settings
powered on (all bits 0), while Register 0x02 has all blocks
powered down (excluding the PLL) such that the clock signal
remains available at CLKOUT1 and CLKOUT2. When the
PWRDWN pin is low, the functional blocks corresponding to
the bits in Register 0x01 are powered down. When the PWRDWN
is high, the functional blocks corresponding to the bits in
Register 0x02 are powered down. PWRDWN immediately affects
the designated functional blocks with minimum digital delay.
Table 23. SPI Registers Associated with Power-Down and
Half-Duplex Power Savings
Address (Hex)
0x01
0x02
0x03
1
With MODE = 1 and CONFIG =1, Register 0x02 default settings are with all blocks
powered off, with RXCLK providing a buffered version of the signal appearing
at OSCIN. This setting results in the lowest power consumption upon power-
up, while still allowing AD9869 to generate the system clock via a crystal.
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7:3
2
1
0
1
are such that Register 0x01 has all blocks
Description
CLK Synthesizer
TxDAC/IAMP
Tx Digital
REF
ADC CML
ADC
PGA Bias
RxPGA
CLK Synthesizer
TxDAC/IAMP
Tx Digital
REF
ADC CML
ADC
PGA Bias
RxPGA
Tx OFF Delay
Rx PWRDWN via
TXEN
Enable Tx PWRDWN
Enable Rx PWRDWN
Comments
PWRDWN = 0.
Default setting is
all functional blocks
powered on.
PWRDWN = 1.
Default setting is
all functional
blocks powered
off excluding PLL.
Half-duplex power
savings.
Rev. 0 | Page 30 of 36
HALF-DUPLEX POWER SAVINGS
Significant power savings can be realized in applications having
a half-duplex protocol, allowing only the Rx path or Tx path to
be operational at one time. The power-savings method depends
on whether the AD9869 is configured for a full-duplex or half-
duplex interface. Functional blocks having fast power-on/power-off
times for the Tx path and Rx path are controlled by the
following bits: TxDAC/IAMP, Tx Digital, ADC, and RxPGA
(see Table 23).
In the case of a full-duplex digital interface (MODE = 1), users
can set Register 0x01 to Register 0x60 and Register 0x02 to
Register 0x05 (or vice versa) such that the Tx path and Rx path are
never powered on simultaneously. The PWRDWN pin can then be
used to control which path is powered on, depending on the burst
type. During a Tx burst, the Rx path PGA and ADC blocks can
typically be powered down within 100 ns, while the Tx path
DAC, IAMP, and digital filter blocks are powered up within
0.5 μs. For an Rx burst, the Tx circuitry can be powered down
within 100 ns, while the Rx circuitry is powered up within 2 μs.
Setting the TXQUIET pin low allows it to be used with the full-
duplex interface to quickly power down the IAMP and disable
the interpolation filter. This is meant to maintain backward
compatibility with the AD9875/AD9876 MxFEs, except that the
TxDAC remains powered if its IOUTP outputs are used. In
most applications, the interpolation filter needs to be flushed
with 0s before or after being powered down. This ensures that
upon power-up, the TxDAC (and IAMP) have a negligible
differential dc offset, thus preventing spectral splatter due to an
impulse transient.
Applications using a half-duplex interface (MODE = 0) can benefit
from an additional power-savings feature available in Register 0x03.
This register is effective only for a half-duplex interface. In addition
to providing power savings for half-duplex applications, this
feature allows the AD9869 to be used in applications that need
only its Rx (or Tx) path functionality through pin strapping,
making a serial port interface (SPI) optional. This feature also
allows the PWRDWN pin to retain its default function as a master
power control, as defined in Table 10.
The default settings for Register 0x03 provide fast power control
of the functional blocks in the Tx signal path and Rx signal path
(outlined previously) using the TXEN pin. The TxDAC remains
powered on in this mode, while the IAMP is powered down.
Significant current savings are typically realized when the
IAMP is powered down.