AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 17

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 11 shows a half-duplex interface with the AD9869 acting
as the master, generating all the required clocks. CLKOUT1
provides a clock equal to the bus data rate that is fed to the
ASIC as well as back to the TXCLK and RXCLK inputs. This
interface has the advantage of reducing the digital ASIC pin
count by three. The ASIC needs only to generate a bus control
signal that controls the data flow on the bidirectional bus.
FULL-DUPLEX MODE
The full-duplex mode interface is selected when the MODE pin
is tied high. It can be used for full- or half-duplex applications.
The digital interface port is divided into two 6-bit ports called
Tx[5:0] and Rx[5:0], allowing simultaneous Tx and Rx operations
for full-duplex applications. In half-duplex applications, the Tx[5:0]
port can also be used to provide a fast update of the RxPGA
during an Rx operation. This feature is enabled by default and
can be used to reduce the required pin count of the ASIC (refer
to RxPGA Control section for details).
DIGITAL ASIC
DIGITAL ASIC
DATA[11:0]
DATA[11:0]
BUS_CTR
Figure 10. Example of a Half-Duplex Digital Interface
Figure 11. Example of a Half-Duplex Digital Interface
DACCLK
ADCCLK
CLKOUT
Tx/Rx
Tx/Rx
CLKIN
RXEN
TXEN
with AD9869 Serving as the Master
with AD9869 Serving as the Slave
FROM
CRYSTAL
OR MASTER CLK
ADIO
[11:0]
ADIO
[11:0]
RXEN
TXEN
TXCLK
RXCLK
OSCIN
RXEN
TXEN
TXCLK
RXCLK
CLKOUT1
OSCIN
AD9869
AD9869
10
10
10
10
TO
Tx DIGITAL
FILTER
TO
Tx DIGITAL
FILTER
FROM
Rx ADC
FROM
Rx ADC
Rev. 0 | Page 17 of 36
In either application, Tx data and Rx data are transferred
between the ASIC and AD9869 in 6-bit (or 5-bit) nibbles at
twice the internal input/output word rates of the Tx interpolation
filter and ADC. Note that the TxDAC update rate must not be
less than the nibble rate. Therefore, the 2× or 4× interpolation
filter must be used with a full-duplex interface.
The AD9869 acts as the master, providing RXCLK as an output
clock that is used for the timing of both the Tx[5:0] and Rx[5:0]
ports. RXCLK always runs at the nibble rate and can be inverted
or disabled via an SPI register. Because RXCLK is derived from
the clock synthesizer, it remains active provided that this
functional block remains powered on. A buffered version of the
signal appearing at OSCIN can also be directed to RXCLK by
setting Bit 2 of Register 0x05. This feature allows the AD9869 to
be completely powered down (including the clock synthesizer)
while serving as the master.
The Tx[5:0] port operates in the following manner with the SPI
register default settings:
1.
2.
3.
4.
TXSYNC
RXCLK
Tx[5:0]
Two consecutive nibbles of the Tx data are multiplexed
together to form a 12-bit data-word in twos complement
format.
The clock appearing on the RXCLK pin is a buffered
version of the internal clock used by the Tx[5:0] port’s
input latch with a frequency that is always twice the ADC
sample rate (2 × f
Data from the Tx[5:0] port is read on the rising edge of this
sampling clock, as illustrated in the timing diagram shown
in Figure 12. Note that TXQUIET must remain high for the
reconstructed Tx data to appear as an analog signal at the
output of the TxDAC or IAMP.
The TXSYNC signal is used to indicate which word
belongs to which nibble. While TXSYNC is low, the first
nibble of every word is read as the most significant nibble.
The second nibble of that same word is read on the
following TXSYNC high level as the least significant
nibble. If TXSYNC is low for more than one clock cycle,
the last transmit data is read continuously until TXSYNC is
brought high for the second nibble of a new transmit word.
This feature can be used to flush the interpolator filters
with zeros. Note that the GAIN signal must be kept low
during a Tx operation.
Figure 12. Tx[5:0] Port Full-Duplex Timing Diagram
Tx0LSB
Tx1MSB
ADC
).
Tx1LSB
t
t
DS
SU
t
Tx2MSB
DH
t
HD
Tx 2 LSB
Tx3LSB
Tx3MSB
AD9869