AD9869-EBZ Analog Devices Inc, AD9869-EBZ Datasheet - Page 28

• Manufacturer Part Number: AD9869-EBZ
• Description: BOARD EVAL FOR AD9869
• Manufacturer: Analog Devices Inc
• Type: ADC + DAC, Codec, Front End for RFr

Specifications of AD9869-EBZ

• Contents: Board
• For Use With/related Products: AD9869
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9869
CLOCK SYNTHESIZER
The AD9869 generates all its internal sampling clocks, as well as
two user-programmable clock outputs appearing at CLKOUT1
and CLKOUT2, from a single reference source (see Figure 32).
The reference source can either be a fundamental frequency or
an overtone quartz crystal connected between OSCIN and
XTAL, with the parallel resonant load components specified by
the crystal manufacturer. It can also be a TTL-level clock
applied to OSCIN with XTAL left unconnected.
C1
Special consideration should be given to the design of crystal
oscillators using the AD9869 internal CMOS inverter. This is
especially true when designing third overtone oscillators where
crystal power dissipation and negative resistance upon start-up
are a few of the issues to consider. For this reason, a 40 MHz or
lower fundamental crystal is preferred with the AD9869.
The CMOS inverter device characteristics are listed in Table 21. It
is recommended to consult with the selected crystal manufacturer
to ensure that a robust design can be realized with the selected
crystal and AD9869 CMOS inverter.
Table 21. CMOS Inverter Device Characteristics
Parameter
RF
gm
Z
C
C
The data rate, f
equal. Therefore, the ADC sample rate, f
f
f
rate refers to the word rate and should not be confused with the
nibble rate in full-duplex interface.
The 2
filter) and a VCO capable of generating an output frequency
that is a multiple of 1, 2, 4, or 8 of its input reference frequency,
f
is between 20 MHz and 80 MHz, and the VCO can operate over
an 80 MHz to 200 MHz span. For the best phase noise/jitter
characteristics, it is advisable to operate the VCO with a
DATA
DATA
OSCIN
OUT
IN
OUT
XTAL
, while the TxDAC update rate is a factor of 1, 2, or 4 of
, depending on the selected interpolation factor. The data
, appearing at OSCIN. The input frequency range of f
C2
M
CLK multiplier contains a PLL (with integrated loop
CLKOUT1
CLKOUT2
OSCIN
XTAL
Nominal
Value
1.2 MΩ
17 mA/V
1.6 kΩ
2.5 pF
2.0 pF
Figure 32. Clock Oscillator and Synthesizer
DATA
, for the Tx and Rx data paths must always be
÷2
÷2
Tolerance %
±25
±20
±50
±25
±25
L
R
MULTIPLIER
2
M
CLK
÷F/2
ADC
÷2
, is always equal to
Description
Feedback resistor.
At midsupply.
At midsupply.
Parasitic capacitance.
Parasitic capacitance.
N
(FULL-DUPLEX ONLY)
RXCLK
TO ADC
TO TxDAC
OSCIN
Rev. 0 | Page 28 of 36
frequency between 100 MHz and 200 MHz. The VCO output
drives the TxDAC directly such that its update rate, f
related to f
where M = 0, 1, 2, or 3.
M is the PLL multiplication factor set in Register 0x04. The
value of M is determined by the Tx path’s word rate, f
digital interpolation factor, F, as shown in the following
equation:
Note that if the reference frequency appearing at OSCIN is
chosen to be equal to the Tx path and Rx path word rates, M is
equal to log
duplex mode (MODE = 1) is a function of the 2
multiplier setting, as well as the interpolation factor, F. Full-
duplex mode requires that RXCLK be equal to 2 × f
data is transferred in nibbles.
The clock source for the ADC can be selected in Register 0x04
as a buffered version of the reference frequency appearing at
OSCIN (default setting) or a divided version of the VCO
output, f
desirable if f
the best jitter/phase noise performance for the ADC sampling
clock. The second option is suitable in cases where f
factor of 2 or 4 less than the f
N, is chosen such that the divided down VCO output is equal to
the ADC sample rate, as shown in the following equation:
where N = 0, 1, or 2.
The CLK synthesizer also has two clock outputs appearing at
CLKOUT1 and CLKOUT2. They are programmable via
Register 0x06. Both outputs can be inverted or disabled. The
voltage levels appearing at these outputs are relative to DRVDD
and remain active during a hardware or software reset. Table 22
shows the SPI registers pertaining to the CLK synthesizer.
Table 22. SPI Registers for CLK Synthesizer
Address (Hex)
0x04
0x06
f
M = log
f
DAC
ADC
DAC
= 2
= f
OSCIN
. The first option is the default setting and most
DAC
2
M
OSCIN
(F). Also note that the RXCLK frequency for full-
2
× f
(F × f
/
2
by the following equation:
OSCIN
N
is equal to f
DATA
Bit
4
3:2
1:0
7:6
5
4
3:2
1
0
/f
OSCIN
ADC
)
ADC
Description
ADC CLK from PLL.
PLL divide factor (N).
PLL multiplication factor (M).
CLKOUT2 divide number.
CLKOUT2 invert.
CLKOUT2 disable.
CLKOUT1 divide number.
CLKOUT1 invert.
CLKOUT1 disable.
. This option typically results in
. In this case, the divider ratio,
M
CLK
DATA
OSCIN
DAC
DATA
, is
because
is a
, and
(7)
(8)
(9)