XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 12

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.2
DC ELECTRICAL CHARACTERISTICS ...................................................................... 292
AC ELECTRICAL CHARACTERISTICS....................................................................... 293
1.0 MICROPROCESSOR INTERFACE TIMING FOR REVISION D SILICON ......................................... 293
2.0 STS-12/STM-4 TELECOM BUS INTERFACE TIMING INFORMATION ............................................. 299
3.0 STS-12/STM-4 PECL INTERFACE TIMING INFORMATION ............................................................. 303
4.0 DS3/E3/STS-1 LIU INTERFACE TIMING INFORMATION.................................................................. 304
P
VDD = 3.3V............................................................................................................................................ 288
VDD (2.5V) ............................................................................................................................................. 288
G
N
DC C
DC C
OWER
O
1.1 MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS INTEL MODE .......................................... 293
1.2 MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS MOTOROLA (68K) MODE ..................... 294
1.3 MICROPROCESSOR INTERFACE TIMING - POWER PC 403 SYNCHRONOUS MODE ............................ 296
1.4 MICROPROCESSOR INTERFACE TIMING - IDT3051/52 MODE.................................................................. 298
2.1 STS-12/STM-4 TELECOM BUS INTERFACE TIMING INFORMATION......................................................... 300
2.2 THE TRANSMIT STS-12/STM-4 TELECOM BUS INTERFACE TIMING ....................................................... 300
2.3 THE RECEIVE STS-12/STM-4 TELECOM BUS INTERFACE TIMING .......................................................... 301
3.1 THE RECEIVE STS-12/STM-4 PECL INTERFACE TIMING........................................................................... 303
3.2 THE TRANSMIT STS-12/STM-4 PECL INTERFACE BLOCK....................................................................... 304
4.1 INGRESS DS3/E3/STS-1 INTERFACE TIMING.............................................................................................. 304
4.2 INGRESS TIMING FOR DS3/E3 APPLICATIONS .......................................................................................... 305
4.3 INGRESS TIMING FOR STS-1/STM-0 APPLICATIONS ................................................................................ 306
4.4 THE EGRESS DS3/E3/STS-1 INTERFACE TIMING....................................................................................... 306
ROUND
F
F
T
F
F
T
F
F
T
F
F
T
F
F
T
F
T
F
T
F
T
F
T
T
T
F
C
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
IGURE
ABLE
IGURE
ABLE
IGURE
ABLE
IGURE
ABLE
ABLE
ABLE
IGURE
ONNECTS
HARACTERISTICS FOR
HARACTERISTICS FOR
S
3: T
9: T
1: T
2: T
4: T
5: T
6: T
7: T
8: T
10: T
11: T
.................................................................................................................................................. 290
UPPLY
14. T
5. A
6. A
7. A
8. A
9. S
10. S
11. S
12. S
13. W
15. W
16. W
17. W
18. W
19. W
M
CHRONOUS
IMING
297
4 T
TION
BLOCK HAS BEEN CONFIGURED TO SAMPLE THE
RISING EDGE OF
F
UPON THE FALLING EDGE OF
E
IMING INFORMATION FOR THE INGRESS
IMING
IMING
IMING
IMING
IMING
IMING
IMING
RAMER
SYNCHRONOUS
SYNCHRONOUS
SYNCHRONOUS
SYNCHRONOUS
YNCHRONOUS
IMING
IMING
GRESS
ODE
IMING RELATIONSHIPS BETWEEN THE
YNCHRONOUS
YNCHRONOUS
YNCHRONOUS
ELECOM
AVEFORMS OF THE
AVEFORMS OF THE
AVEFORMS OF THE
AVEFORMS OF THE
AVEFORMS OF THE
AVEFORMS OF THE
......................................................................................................................................... 290
........................................................................................................................................................................... 305
P
I
I
I
I
I
I
I
I
NFORMATION FOR THE
NFORMATION FOR THE
NFORMATION FOR THE
NFORMATION FOR THE
NFORMATION FOR THE
NFORMATION FOR THE
NFORMATION FOR THE
NFORMATION FOR THE
......................................................................................................................................................................... 294
INS
I
I
NFORMATION FOR THE
NFORMATION FOR THE
B
D
LOCK HAS BEEN CONFIGURED TO SAMPLE THE
IRECTION
M
B
............................................................................................................................... 288
US
ODE
M
DS3/E3/STS_1_CLOCK_IN ............................................................................................................ 305
I
M
M
M
M
M
M
M
NTERFACE
ODE
........................................................................................................................................................ 295
ODE
ODE
ODE
ODE
ODE
ODE
ODE
TTL
LVPECL I/O .................................................................................................. 292
).................................................................................................................................................... 307
DS3/E3/STS-1
DS3/E3/STS-1
3 - IBM P
S
S
S
T
1 - I
1 - I
2 - M
2 - M
3 - IBM P
4 - IDT3051/52 I
4 - IDT3051/52 I
RANSMIT
IGNALS THAT ARE OUTPUT VIA THE
IGNALS THAT ARE
IGNALS THAT ARE
INPUT
NTEL
NTEL
........................................................................................................................................ 301
DS3/E3/STS_1_CLOCK_IN ........................................................................................... 306
M
OTOROLA
OTOROLA
M
M
M
T
R
R
T
ICROPROCESSOR
I
I
RANSMIT
RANSMIT
ECEIVE
ECEIVE
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
NGRESS
NGRESS
OWER
/CMOS
STS-12/STM-4 PECL I
T
T
OWER
YPE
YPE
DS3/
PC 403 I
T
SIGNALS THAT ARE INPUT TO THE
SIGNALS THAT ARE OUTPUT FROM THE
STS-12/STM-4 T
STS-12/STM-4 PECL I
68K P
68K P
P
P
PC 403 I
X
STS-12/STM-4 T
STS-12/STM-4 PECL I
DS3/E3/STS-1 LIU I
DS3/E3/STS-1 LIU I
ROGRAMMED
ROGRAMMED
SBFP
NTERFACE
NTERFACE
I
I
NPUT VIA THE
NPUT VIA THE
OUTPUT
E
3/STS-1 LIU
DS3/E3/STS_1_DATA_IN
ROGRAMMED
ROGRAMMED
NTERFACE
INPUT PIN AND THE
I
NTERFACE
I
I
NTERFACE
I
NTERFACE
NTERFACE WHEN CONFIGURED TO OPERATE IN THE
NTERFACE
T
T
II
............................................................................. 292
IMING
IMING
I/O T
I/O T
DS3/E3/STS_1_DATA_IN
R
R
ELECOM
NTERFACE
ELECOM
ECEIVE
ECEIVE
INTERFACE FOR
T
T
,
I/O T
I/O T
(W
(R
IMING
IMING
,
T
WHEN CONFIGURED TO OPERATE IN THE
,
IMING
RANSMIT
WHEN CONFIGURED TO OPERATE IN THE
IMING
WHEN CONFIGURED TO OPERATE IN THE
NTERFACE FOR
NTERFACE FOR
EAD
RITE
NTERFACE
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
NTERFACE
IMING
IMING
B
(W
(R
STS-12/STM-4 T
STS-12/STM-4 PECL I
(W
T
C
B
US
(R
C
X
S
EAD
YCLE
US
RITE
RITE
YCLE
STS-12/STM-4 T
A_CLK
IGNALS
EAD
I
(W
(R
NTERFACE
DS3/E3/STS-1 LIU
I
NTERFACE
C
EAD
) .................................................................. 299
AND
RITE
C
C
)................................................................. 298
................................................................... 303
DS3/E3
YCLE
C
YCLE
................................................................. 304
YCLE
YCLE
DS3/E3/STS-1 LIU I
DS3/E3 A
STS-1/STM-0 A
.............................................................. 304
OUTPUT PIN WITHIN THE
C
DS3/E3/STS_1_NEG_IN
C
YCLE
)......................................................... 293
YCLE
) ....................................................... 293
)....................................................... 296
) ...................................................... 297
....................................................... 302
APPLICATIONS WHEN THE
AND
..................................................... 301
ELECOM
) ................................................. 295
) ................................................ 294
ELECOM
PPLICATIONS AND WHEN THE
DS3/E3/STS_1_NEG_IN
NTERFACE
INTERFACE IN THE INGRESS DIREC
B
PPLICATIONS
US
B
US
I
NTERFACE
NTERFACE
IBM P
........................... 303
M
I
T
I
IDT3051/52 M
NTERFACE
NTEL
RANSMIT
OTOROLA
INPUT PINS UPON THE
OWER
XRT94L43
A
................. 306
DS3/E3
.............. 302
SYNCHRONOUS
(
IN THE
STS-12/STM-
PC403 M
......... 300
(68K) A
INPUT PINS
ODE
DS3/E3
R
FRAMER
ECEIVE
SYN
299
ODE
-
-
/