XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 20

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.2
SONET/SDH SERIAL LINE INTERFACE PINS
P
K3
L4
L3
T3
IN
#
RXL_DATA_N
RXL_DATA_R_P
RXL_DATA_R_N
TXL_CLKI_P
S
IGNAL
N
AME
I/O
I
I
I
I
LVPECL
LVPECL
LVPECL
LVPECL
S
T
IGNAL
YPE
Receive STS-12/STM-4 Data - Negative Polarity PECL Input:
This input pin, along with RXL_DATA_P functions as the Recov-
ered Data Input, from a System back-plane or an Optical Trans-
ceiver. The Receive STS-12/STM-4 Interface block will sample the
data applied to these input pins, upon the rising edge of the
RXL_CLKL_P (and the falling edge of the RXL_CLKL_N) signals.
N
Receive STS-12/STM-4 Data - Positive Polarity PECL Input -
Redundant Port:
This input pin, along with RXL_DATA_R_N functions as the Recov-
ered Data Input, from a System back-plane or an Optical Trans-
ceiver. The Receive STS-12/STM-4 Interface block will sample the
data applied to these input pins, upon the rising edge of the
RXL_CLKL_R_P (and the falling edge of the RXL_CLKL_R_N) sig-
nals.
N
Receive STS-12/STM-4 Data - Negative Polarity PECL Input -
Redundant Port:
This input pin, along with RXL_DATA_R_P functions as the Recov-
ered Data Input, from a System back-plane or an Optical Trans-
ceiver. The Receive STS-12/STM-4 Interface block will sample the
data applied to these input pins, upon the rising edge of the
RXL_CLKL_R_P (and the falling edge of the RXL_CLKL_R_N) sig-
nals.
N
Transmit Reference Clock - Positive Polarity PECL Input:
This input pin, along with TxL_CLKI_N can be configured to func-
tion as the timing source for the STS-12/STM-4 Transmit Interface
Block.
If these two input pins are configured to function as the timing
source, then a 622.08MHz clock signal must be applied to these
input pins in the form of a PECL signal. These two inputs can be
configured to function as the timing source by writing the appropri-
ate data into the Interface Control Register - Byte 2 (Indirect
Address = 0x00, 0x31), (Direct Address = 0x0131).
OTE
OTE
OTE
: For APS (Automatic Protection Switching) purposes, this
: For APS (Automatic Protection Switching) purposes, this
: For APS (Automatic Protection Switching) purposes, this
14
input pin, along with RXL_DATA_P functions as the
Primary Receive Data Input Port.
input pin, along with RXL_DATA_R_N functions as the
Redundant Receive Data Input Port.
input pin, along with RXL_DATA_R_N functions as the
Redundant Receive Data Input Port.
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
D
ESCRIPTION
XRT94L43