XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 307
XRT94L43IB-F
Manufacturer Part Number
XRT94L43IB-F
Description
IC MAPPER SONET/SDH OC12 516BGA
Manufacturer
Exar Corporation
Datasheet
1.XRT94L43IB.pdf
(328 pages)
Specifications of XRT94L43IB-F
Applications
Network Switches
Interface
Bus
Voltage - Supply
2.5V, 3.3V
Package / Case
516-BBGA
Mounting Type
Surface Mount
Product
Mapper
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XRT94L43IB-F
Manufacturer:
Exar Corporation
Quantity:
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Part Number:
XRT94L43IB-F
Manufacturer:
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Quantity:
20 000
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XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
The TxSBFP input signal is sampled upon the rising edge of TxA_CLK by the Transmit STS-12/STM-4
Telecom Bus Interface circuitry, as illustrated below in
N
Table 5
In the Receive STS-12/STM-4 Telecom Bus Interface, all of the signals (which are input via this Bus Interface)
are sampled upon the rising edge of RxD_CLK (77.76MHz clock signal).
Figure 15
be received by the Receive STS-12/STM-4 Telecom Bus Interface.
F
T
2.3
RANSMIT
OTE
IGURE
S
YMBOL
t
t
t
t
t
5A
5B
: The value for t
1
4
5
14. T
presents information on the Timing parameters for the Transmit STS-12/STM-4 Telecom Bus Interface.
The Receive STS-12/STM-4 Telecom Bus Interface Timing
STS-12/STM-4 T
T
presents an illustration of the waveforms and the timing parameters (t2 and t3) of the signals that will
TxA _CLK
TxA _D[7:0]
Rising edge of TxA_CLK to updates in TxA_D[7:0], TxA_PL,
TxA_C1J1 and TxA_DP
TxSBFP Set-up time to rising edge of TxA_CLK
TxA_CLK rising edge to TxSBFP Hold time
TxSBFP Set-up time to rising edge of REFCLK
Rising edge of REFCLK to TxSBFP Hold Time
ABLE
REFCLK
TxSBFP
IMING RELATIONSHIPS BETWEEN THE
5: T
4
, t
IMING
5
, t
5A
I
ELECOM
and t
NFORMATION FOR THE
Data
5B
D
can be found in
B
ESCRIPTION
US
t
5A
t
A1
4
I
NTERFACE
t
5B
t
5
T
A1
Table 5
T
X
RANSMIT
SBFP
301
Figure
.
INPUT PIN AND THE
STS-12/STM-4 T
14.
Data
3.7ns
8.5ns
M
0ns
5ns
0ns
Data
IN
ELECOM
T
.
X
A_CLK
B
US
Data
OUTPUT PIN WITHIN THE
T
YP
I
NTERFACE
.
REV. 1.0.2
9.5ns
M
AX
.
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