XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 310

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.2
The outbound STS-12/STM-4 data (from the Transmit STS-12/STM-4 PECL Interface block) is updated upon
the rising edge of TxLCLKO_p/TxLCLKO_n via the TxLData_p/TxLData_n output pins.
Table 8
N
The user should be aware of the following things about the Ingress DS3/E3/STS-1 Interface Timing.
F
3.2
4.0 DS3/E3/STS-1 LIU INTERFACE TIMING INFORMATION
4.1
OTE
IGURE
S
b. If a given channel is configured to operate in the STS-1/STM-0 Mode, then the Receive STS-1 TOH Pro-
a. If a given channel is configured to operate in the DS3/E3 Mode, then the DS3/E3 Framer block can be
c. Further, if a given channel is configured to operate in the STS-1/STM-0 Mode, then the Receive STS-1
YMBOL
t
: These timing requirements apply to both the Primary and the Redundant Transmit STS-12/STM-4 PECL Interface
8
configured to sample the DS3/E3/STS_1_DATA_IN and the DS3/E3/STS_1_NEG_IN input pins upon
either the rising or falling edge of DS3/E3/STS_1_CLOCK.
cessor block will be operating in the Single-Rail Mode (e.g., the Receive STS-1 TOH Processor block will
ONLY sample the DS3/E3/STS_1_DATA_IN input signal. It will not sample the DS3/E3/STS_1_NEG_IN
input signal.
TOH Processor block can ONLY be configured to sample the DS3/E3/STS_1_DATA_IN input signal,
upon the rising edge of DS3/E3/STS_1_CLOCK_IN. The Receive STS-1 TOH Processor block CAN-
NOT be configured to sample the DS3/E3/STS_1_DATA_IN input signal upon the falling edge of DS3/
E3/STS_1_CLOCK_IN.
block.
17. W
Ingress DS3/E3/STS-1 Interface Timing
presents information on the Timing Parameter for the Transmit STS-12/STM-4 PECL Interface
The Transmit STS-12/STM-4 PECL Interface Block
Rising edge of TxLCLKO to TxLDATA out delay
TxLCLKO_n
TxLCLKO_p
T
AVEFORMS OF THE
TxLData_p
TxLData_n
ABLE
8: T
IMING
I
NFORMATION FOR THE
T
D
RANSMIT
ESCRIPTION
STS-12/STM-4 PECL I
T
304
RANSMIT
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
STS-12/STM-4 PECL I
NTERFACE
600ps
M
IN
.
S
IGNALS
t
8
NTERFACE
800ps
T
YP
.
XRT94L43
M
1ns
AX
.