XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 241
XRT94L43IB-F
Manufacturer Part Number
XRT94L43IB-F
Description
IC MAPPER SONET/SDH OC12 516BGA
Manufacturer
Exar Corporation
Datasheet
1.XRT94L43IB.pdf
(328 pages)
Specifications of XRT94L43IB-F
Applications
Network Switches
Interface
Bus
Voltage - Supply
2.5V, 3.3V
Package / Case
516-BBGA
Mounting Type
Surface Mount
Product
Mapper
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XRT94L43IB-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XRT94L43IB-F
Manufacturer:
EXAR/艾科嘉
Quantity:
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XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
STS-3/STM-1 TELECOM BUS INTERFACE - RECEIVE DIRECTION
P
G25
IN
#
STS3RxD_DP_1
RxDS3FP_5
TxSTS1FP_5
S
IGNAL
N
AME
I/O
O
S
CMOS STS-3/STM-1 Receive (Drop) Telecom Bus - Parity Output
T
IGNAL
YPE
Pin - Channel 1; DS3/E3 Frame Synchronizer Framing
Pulse Output Pin - Channel 5:
The function of this output pin depends upon whether or not
theSTS-3/STM-1 Telecom Bus Interface for Channel 1 has
been enabled.
If STS-3/STM-1 Telecom Bus (Channel 1) has been enabled
- STS-3/STM-1 Receive Telecom Bus - Parity Output Pin:
This output pin can be configured to function as one of the fol-
lowing.
1. The EVEN or ODD parity value of the bits which are output
via the STS3RXD_D_1[7:0] output pins.
2. The EVEN or ODD parity value of the bits which are being
output via the STS3RXD_D_1[7:0] output pins and the states
of the STS3RXD_PL_1 and STS3RXD_C1J1_1 output pins.
This output pin will ultimately be used (by drop-side circuitry) to
verify the verify of the data which is output via the STS-3/STM-
1 Telecom Bus Interface associated with Channel 1.
N
If STS-3/STM-1 Telecom Bus (Channel 1) is disabled -
RxDS3FP_5 (Receive DS3 Frame Pulse Input/Output -
Channel 5):
If the STS-3/STM-1 Telecom Bus (Channel 1) is disabled and if
the DS3/E3 Framer block is enabled then this pin will function
as the Receiving Framing Reference output pin. In this mode,
the Frame Synchronizer block (associated with Channel 5) will
pulse this output pin "High" for one DS3/E3 bit-period, coinci-
dent with the first bit (within a given DS3 or E3 frame) being
output via the DS3/E3/STS1_Data_OUT_5 output pin.
N
235
OTE
OTE
: Any one of these configuration selections can be made
: This pin is inactive if the Frame Synchronizer block,
by writing the appropriate value into the Telecom Bus
Control Register (Indirect Address = 0x00, 0x3A),
(Direct Address = 0x013A).
associated with Channel 5 is by-passed.
D
ESCRIPTION
REV. 1.0.2
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