XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 314

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.2
Table 14
Egress Direction) for STS-1/STM-0 Applications.
This section presents the timing requirements for the STS-3/STM-1 Telecom Bus Interface. In particular this
section indicates the following.
In contrast to the names that are given to the Transmit and Receive STS-3/STM-1 Telecom Bus Interface, the
Transmit STS-3/STM-1 Telecom Bus interface will have the responsibility of receiving (in lieu of transmitting)
STS-3/STM-1 data from some remote entity over a Telecom Bus Interface that is clocked at 19.44MHz.
Likewise, the Receive STS-3/STM-1 Telecom Bus Interface will have the responsibility of transmitting (in lieu of
receiving) STS-3/STM-1 data to some remote entity over a Telecom Bus Interface that is also clocked at
19.44MHz.
In the Receive STS-3/STM-1 Telecom Bus Interface, all of the signals (which are output via this Bus Interface)
are updated upon the rising edge of RxD_CLK (19.44MHz clock signal).
4.6
5.0 STS-3/STM-1 TELECOM BUS INTERFACE TIMING INFORMATION
5.1
5.2
S
b. The clock to output delays (from the rising edge of RxD_CLK to the instant that the RxD_D[7:0],
d. The set-up time requirements (from an update in the TxA_D[7:0], TxA_PL, TxA_C1J1, TxA_ALARM and
a. Identifies which edge of RxD_CLK in which the RxD_D[7:0], RxD_PL, RxD_C1J1, RxD_ALARM and
c. Identifies which edge of TxA_CLK that the TxA_D[7:0], TxA_PL, TxA_C1J1 and TxA_DP input pins are
e. The hold-time requirements (from the rising edge of TxA_CLK to a change in the TxA_D[7:0], TxA_PL,
YMBOL
t
11
T
RxD_DP output pins are updated on.
RxD_PL, RxD_C1J1, RxD_ALARM and RxD_DP output pins are updated.
sampled on.
TxA_DP input signals to the rising edge of TxA_CLK).
TxA_C1J1, TxA_ALARM and TxA_DP input signals)
ABLE
Egress Timing for STS-1/STM-0 Applications
STS-3/STM-1 Telecom Bus Interface Timing Information
The Receive STS-3/STM-1 Telecom Bus Interface Timing
presents information on the Timing parameters for the DS3/E3/STS-1 LIU Interface Signals (in the
14: T
Rising edge of DS3/E3/STS_1_CLK_OUT to DS3/
E3/STS_1_DATA_OUT output delay
IMING
I
NFORMATION FOR THE
D
ESCRIPTION
E
GRESS
A
PPLICATIONS
308
DS3/E3/STS-1 LIU I
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
M
0ns
IN
.
NTERFACE FOR
T
YP
.
STS-1/STM-0
XRT94L43
M
3ns
AX
.