XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 81
XRT94L43IB-F
Manufacturer Part Number
XRT94L43IB-F
Description
IC MAPPER SONET/SDH OC12 516BGA
Manufacturer
Exar Corporation
Datasheet
1.XRT94L43IB.pdf
(328 pages)
Specifications of XRT94L43IB-F
Applications
Network Switches
Interface
Bus
Voltage - Supply
2.5V, 3.3V
Package / Case
516-BBGA
Mounting Type
Surface Mount
Product
Mapper
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
XRT94L43IB-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XRT94L43IB-F
Manufacturer:
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XRT94L43
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
STS-3/STM-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION
AB19
P
IN
#
STS3TxA_D_3_3
DS3/E3/
STS1_Data_IN_7
TxSBData_3
S
IGNAL
N
AME
I/O
I
S
T
IGNAL
TTL
YPE
Transmit STS-3/STM-1 Telecom Bus - Channel 3 - Input Data Bus
Pin Number 3/DS3/E3 Framer or Receive STS-1 TOH Processor
block line interface input Pin - Channel 7:
The function of this pin depends upon whether or not theSTS-3/STM-
1 Telecom Bus Interface, associated with Channel 3 is enabled.
If STS-3/STM-1 Telecom Bus (Channel 3) has been enabled -
STS-3/STM-1 Transmit Telecom Bus - Input Data Bus Pin Num-
ber 3: STS3TxA_D_3_3:
STS3TxA_D_3[2:0] function as the STS-3/STM-1 Transmit (Add)
Telecom Bus - Input Data Bus for Channel 3. The STS-3/STM-1 Tele-
com Bus interface will sample and latch this pin upon the falling edge
of STS3TxA_CLK_3.
If STS-3/STM-1 Telecom Bus (Channel 3) is disabled - DS3/E3/
STS1_DATA_IN - DS3/E3/STS-1 Line Interface Data Input - Chan-
nel 7:
This input accepts single-rail, recovered DS3, E3 or STS-1 data
(from a DS3/E3/STS-1 LIU IC). This input pin should be connected to
the RPOS output of the DS3/E3/STS-1 LIU IC (corresponding to
channel 7).
By default, the data that is applied to this input pin will be latched into
the XRT94L43 upon the falling edge of the DS3/E3/STS1_CLK_IN_7
signal pin number AA19.
For DS3/E3 Applications
The XRT94L43 can be configured to latch this input signal upon the
rising edge of the DS3/E3/STS1_CLK_IN_7 signal by setting Bit 1
(DS3/E3/STS1_CLK_IN Invert), within the I/O Control Register -
Channel 7 (Indirect Address = 0x8E, 0x01), (Direct Address =
0x8F01) to a "1".
For STS-1 Applications
The XRT94L43 can not be configured to sample the DS3/E3/
STS1_DATA_IN_7 signal upon the rising edge of DS3/E3/
STS1_CLK_IN_7.
This input pin along with STS3TxA_D_3[7:4] and
75
D
ESCRIPTION
REV. 1.0.2
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