XRT94L43IB-F Exar Corporation, XRT94L43IB-F Datasheet - Page 238

• Manufacturer Part Number: XRT94L43IB-F
• Description: IC MAPPER SONET/SDH OC12 516BGA
• Manufacturer: Exar Corporation

Specifications of XRT94L43IB-F

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 2.5V, 3.3V
• Package / Case: 516-BBGA
• Mounting Type: Surface Mount
• Product: Mapper
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.2
STS-3/STM-1 TELECOM BUS INTERFACE - RECEIVE DIRECTION
AC20
P
IN
#
STS3RxD_C1J1_2
RxDS3FP_10
TxSTS1FP_10
RxSBFrame_2
S
IGNAL
N
AME
I/O
O
S
CMOS STS-3/STM-1 Receive Telecom Bus - C1/J1 Byte Phase
T
IGNAL
YPE
Indicator Output Signal - Channel 2; DS3/E3 Frame Syn-
chronizer Framing Pulse Output Pin - Channel 10:
The function of this output pin depends upon whether or not
theSTS-3/STM-1 Telecom Bus Interface for Channel 2 has
been enabled.
If STS-3/STM-1 Telecom Bus (Channel 2) has been enabled
- STS-3/STM-1 Receive Telecom Bus - C1/J1 Byte Phase
Indicator Output Signal:
This output pin pulses "High" under the following two condi-
tions.
1. Whenever the C1 byte is being output via the
STS3RxD_D_2[7:0] output, and
2. Whenever the J1 byte is being output via the
STS3RxD_D_2[7:0] output.
N
If STS-3/STM-1 Telecom Bus (Channel 2) is disabled -
RxDS3FP_10 (Receive DS3 Frame Pulse Input/Output -
Channel 10):
If the STS-3/STM-1 Telecom Bus (Channel 2) is disabled and if
the DS3/E3 Framer block is enabled then this pin will function
as the Receiving Framing Reference output pin. In this mode,
the Frame Synchronizer block (associated with Channel 10)
will pulse this output pin "High" for one DS3/E3 bit-period, coin-
cident with the first bit (within a given DS3 or E3 frame) being
output via the DS3/E3/STS1_Data_OUT_10 output pin.
N
232
OTES
OTE
1. The STS-3/STM-1 Receive (Drop) Telecom Bus
2. The STS-3/STM-1 Receive (Drop) Telecom Bus
: This pin is inactive if the Frame Synchronizer block,
:
associated with Channel 10 is by-passed.
(associated with Channel 2) will indicate that it is
transmitting the C1 byte (via the STS3RxD_D_2[7:0]
output pins), by pulsing this output pin "High" (for one
period of STS3RXD_CLK_2) and keeping the
STS3RXD_PL_2 output pin pulled "Low".
(associated with Channel 2) will indicate that it is
transmitting the J1 byte (via the STS3RXD_D_2[7:0]
output pins), by pulsing this output pin "High" (for one
period
STS3TXD_PL_2 output pin is pulled "High".
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
of
D
STS3RXD_CLK_2)
ESCRIPTION
XRT94L43
while
the