LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 294
![FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M20SE-5FN256C
Manufacturer Part Number
LFE2M20SE-5FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20SE-5FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20SE-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA
Lattice Semiconductor
Number
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO
VCCIO
VCCIO
AK29
AH30
AG27
AD25
AG28
AG30
AG29
AC24
AE26
AB23
AD26
AE29
AE30
AD29
AC25
AD30
AA22
AC26
AA23
AB22
AC27
AC28
AC29
AC30
AB30
AA30
AB29
AB28
AB26
AB27
AA29
AJ29
AJ30
AF27
AF28
AF29
AF30
Ball
Y22
Y23
Y24
Y25
-
LRC_SQ_VCCRX0
LRC_SQ_HDINN0
LRC_SQ_HDINP0
LRC_SQ_VCCIB0
D0/SPIFASTN***
RLM0_PLLCAP
DI/CSSPI0N***
BUSY/SISPI***
DOUT/CSON/
PROGRAMN
D7/SPID0***
CSSPI1N***
WRITEN***
Function
Ball/Pad
GNDIO8
CS1N***
GNDIO8
GNDIO3
GNDIO3
VCCIO8
VCCIO8
VCCIO3
CSN***
PR65B
PR65A
PR64B
PR64A
PR63B
PR63A
PR62B
PR62A
PR60B
PR60A
DONE
CFG2
CFG1
CFG0
CCLK
INITN
D1***
D2***
D3***
D4***
D5***
D6***
NC
NC
NC
NC
NC
-
LFE2M50E/SE
Bank
13
13
13
13
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
-
-
-
-
-
-
RLM0_GDLLC_IN_A**
RLM0_GPLLC_IN_A**
RLM0_GDLLT_IN_A**
RLM0_GPLLT_IN_A**
RLM0_GDLLC_FB_A
RLM0_GPLLC_FB_A
RLM0_GDLLT_FB_A
RLM0_GPLLT_FB_A
Dual Function
Differential
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
4-191
C
C
C
C
T
T
T
T
LRC_SQ_VCCRX0
LRC_SQ_HDINN0
LRC_SQ_HDINP0
LRC_SQ_VCCIB0
D0/SPIFASTN***
RLM0_PLLCAP
DI/CSSPI0N***
BUSY/SISPI***
DOUT/CSON/
PROGRAMN
D7/SPID0***
CSSPI1N***
WRITEN***
Function
Ball/Pad
GNDIO8
CS1N***
VCCIO8
GNDIO8
VCCIO8
GNDIO3
VCCIO3
GNDIO3
VCCIO3
CSN***
PR85B
PR85A
PR84B
PR84A
PR83B
PR83A
PR82B
PR82A
PR81B
PR81A
PR80B
PR80A
PR79B
PR79A
PR78B
DONE
CFG2
CFG1
CFG0
CCLK
INITN
D1***
D2***
D3***
D4***
D5***
D6***
LatticeECP2/M Family Data Sheet
Bank
13
13
13
13
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
LFE2M70E/SE
RLM0_GDLLC_IN_A**/RDQ82 C (LVDS)*
RLM0_GPLLC_IN_A**/RDQ82
RLM0_GPLLT_FB_A/RDQS82
RLM0_GDLLT_IN_A**/RDQ82
RLM0_GPLLT_IN_A**/RDQ82
RLM0_GDLLC_FB_A/RDQ82
RLM0_GPLLC_FB_A/RDQ82
RLM0_GDLLT_FB_A/RDQ82
Dual Function
Pinout Information
RDQ82
RDQ82
RDQ82
RDQ82
RDQ82
RDQ82
RDQ82
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
T
T
T
T
T
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