LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 346
![FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M20SE-5FN256C
Manufacturer Part Number
LFE2M20SE-5FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20SE-5FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20SE-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA
Lattice Semiconductor
Number
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
M28
M27
M26
M32
M31
M30
Ball
K34
K33
K30
K29
H33
H34
H31
H32
H30
B33
C33
B34
C32
B32
A33
C34
A32
B31
A31
L27
L34
L33
L32
L31
L28
L29
L30
J34
J33
J32
J31
J30
J29
J27
J28
-
URC_SQ_HDOUTP0
URC_SQ_HDOUTN0
URC_SQ_HDOUTN1
URC_SQ_VCCRX0
URC_SQ_VCCOB0
URC_SQ_VCCTX0
URC_SQ_VCCTX1
URC_SQ_HDINP0
URC_SQ_HDINN0
URC_SQ_VCCIB0
Function
Ball/Pad
GNDIO2
GNDIO2
GNDIO2
GNDIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR19A
PR18B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
PR14A
PR13B
PR13A
PR11B
PR11A
XRES
PR9B
PR9A
-
LFE2M70E/SE
Bank
12
12
12
12
12
12
12
12
12
12
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
-
-
-
-
-
RUM0_SPLLC_IN_A/RDQ15
RUM0_SPLLT_IN_A/RDQ15
Dual Function
VREF2_2
VREF1_2
RDQS15
RDQ28
RDQ28
RDQ28
RDQ28
RDQ28
RDQ28
RDQ15
RDQ15
RDQ15
RDQ15
RDQ15
RDQ15
RDQ15
RDQ15
RDQ15
RDQ15
RDQ15
Differential
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
4-243
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
URC_SQ_HDOUTP0
URC_SQ_HDOUTN0
URC_SQ_HDOUTN1
URC_SQ_VCCRX0
URC_SQ_VCCOB0
URC_SQ_VCCTX0
URC_SQ_VCCTX1
URC_SQ_HDINP0
URC_SQ_HDINN0
URC_SQ_VCCIB0
Function
Ball/Pad
GNDIO2
GNDIO2
GNDIO2
GNDIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
PR30B
PR30A
PR29B
PR29A
PR28B
PR28A
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR19A
PR18B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
PR14A
PR13B
PR13A
PR11B
PR11A
XRES
PR9B
PR9A
LatticeECP2/M Family Data Sheet
LFE2M100E/SE
Bank
12
12
12
12
12
12
12
12
12
12
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
-
-
RUM0_SPLLC_IN_A/RDQ15
RUM0_SPLLT_IN_A/RDQ15
Dual Function
Pinout Information
VREF2_2
VREF1_2
RDQS15
RDQ32
RDQ32
RDQ23
RDQ23
RDQ23
RDQ23
RDQ23
RDQ23
RDQ15
RDQ15
RDQ15
RDQ15
RDQ15
RDQ15
RDQ15
RDQ32
RDQ32
RDQ32
RDQ32
RDQ23
RDQ23
RDQ15
RDQ15
RDQ15
RDQ15
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
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