LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 89
LFE2M20SE-5FN256C
Manufacturer Part Number
LFE2M20SE-5FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20SE-5FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20SE-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
DLL Timing
f
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1. CLKOP runs at the same frequency as the input clock.
2. CLKOS minimum frequency is obtained with divide by 4.
3. This is intended to be a “path-matching” design guideline and is not a measurable specification.
Parameter
REF
FB
CLKOP
CLKOS
PJIT
CYJIT
DUTY
DUTYTRD
DUTYCIR
SKEW
PWH
PWL
INSTB
LOCK
RSWD
PA
RANGE1
RANGE4
3
1
2
Input reference clock frequency (on-chip or off-chip)
Feedback clock frequency (on-chip or off-chip)
Output clock frequency, CLKOP
Output clock frequency, CLKOS
Output clock period jitter (clean input)
Output clock cycle to cycle jitter (clean input)
Output clock duty cycle (at 50% levels, 50% duty cycle input clock,
50% duty cycle circuit turned off, time reference delay mode)
Output clock duty cycle (at 50% levels, arbitrary duty cycle input
clock, 50% duty cycle circuit enabled, time reference delay mode)
Output clock duty cycle (at 50% levels, arbitrary duty cycle input
clock, 50% duty cycle circuit enabled, clock injection removal
mode)
Output clock to clock skew between two outputs with the same
phase setting
Input clock minimum pulse width high (at 80% level)
Input clock minimum pulse width low (at 20% level)
Input clock period jitter
DLL lock time
Digital reset minimum pulse width (at 80% level)
Delay step size
Max. delay setting for single delay block (144 taps)
Max. delay setting for four chained delay blocks
Over Recommended Operating Conditions
Description
3-37
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
18,500
2.376
9.504
Min.
16.5
100
100
100
750
750
25
35
40
40
—
—
3
Typ.
42
24
—
—
—
—
—
—
—
—
—
—
—
6
34.214
+/-250
8.553
Max.
59.4
500
500
500
500
250
250
100
65
60
60
—
—
—
—
ps p-p
ps p-p
cycles
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ns
ps
ns
ns
%
%
%
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