LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 92
![FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M20SE-5FN256C
Manufacturer Part Number
LFE2M20SE-5FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20SE-5FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20SE-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 3-12. Transmitter and Receiver Block Diagram
HDOUTPi
HDOUTNi
HDINPi
HDINNi
Transmitter
Receiver
REFCLK
EQ
TX PLL
SERDES
REFCLK
CDR
Serializer
8:1/10:1
Transmit Clock
T4
Deserializer
R1
1:8/1:10
SERDES Bridge
R2
BYPASS
Polarity
Adjust
BYPASS
Polarity
Adjust
T3
Recovered Clock
3-40
BYPASS
R3
WA
Encoder
BYPASS
BYPASS
DEC
PCS
T2
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
R4
BYPASS
Elastic
Buffer
FIFO
R5
FPGA Bridge
Sample
Down
FIFO
Sample
R6
FIFO
Up
BYPASS
T1
FPGA Core
FPGA
EBRD Clock
Receive Data
FPGA
Receive Clock
Transmit Data
FPGA
Transmit Clock
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