LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 298
![FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M20SE-5FN256C
Manufacturer Part Number
LFE2M20SE-5FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20SE-5FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20SE-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA
Lattice Semiconductor
Number
GNDIO
GNDIO
VCCIO
VCCIO
Ball
G25
G23
C30
A29
B30
B29
C27
A26
A27
B26
C26
B25
C25
A25
C29
B28
C28
A28
B24
E24
D24
C24
A20
C20
B20
C19
A23
C23
B23
C22
B22
A21
A22
C21
B19
B18
A19
C18
D23
E21
D26
E26
F26
F24
F25
URC_SQ_VCCAUX33
URC_SQ_HDOUTN0
URC_SQ_HDOUTN1
URC_SQ_HDOUTN2
URC_SQ_HDOUTN3
URC_SQ_HDOUTP0
URC_SQ_HDOUTP1
URC_SQ_REFCLKN
URC_SQ_HDOUTP2
URC_SQ_HDOUTP3
URC_SQ_REFCLKP
URC_SQ_VCCRX0
URC_SQ_VCCOB0
URC_SQ_VCCOB1
URC_SQ_VCCRX1
URC_SQ_VCCRX2
URC_SQ_VCCOB2
URC_SQ_VCCOB3
URC_SQ_VCCRX3
URC_SQ_VCCTX0
URC_SQ_VCCTX1
URC_SQ_VCCTX2
URC_SQ_VCCTX3
URC_SQ_HDINP0
URC_SQ_HDINN0
URC_SQ_HDINN1
URC_SQ_HDINP1
URC_SQ_HDINP2
URC_SQ_HDINN2
URC_SQ_HDINN3
URC_SQ_HDINP3
URC_SQ_VCCIB0
URC_SQ_VCCIB1
URC_SQ_VCCIB2
URC_SQ_VCCIB3
URC_SQ_VCCP
Function
Ball/Pad
GNDIO2
GNDIO1
VCCIO2
VCCIO2
PR11B
PR11A
PT73B
PT73A
PT72B
PT72A
PR9B
PR9A
XRES
LFE2M50E/SE
Bank
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
2
2
2
2
2
1
1
1
1
-
-
-
-
RUM0_SPLLC_IN_A
RUM0_SPLLT_IN_A
Dual Function
VREF2_2
VREF1_2
Differential
C (LVDS)*
T (LVDS)*
4-195
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
URC_SQ_VCCAUX33
URC_SQ_HDOUTP0
URC_SQ_HDOUTN0
URC_SQ_HDOUTN1
URC_SQ_HDOUTP1
URC_SQ_HDOUTP2
URC_SQ_HDOUTN2
URC_SQ_HDOUTN3
URC_SQ_HDOUTP3
URC_SQ_REFCLKN
URC_SQ_REFCLKP
URC_SQ_VCCOB0
URC_SQ_VCCOB1
URC_SQ_VCCOB2
URC_SQ_VCCOB3
URC_SQ_VCCRX0
URC_SQ_VCCTX0
URC_SQ_VCCTX1
URC_SQ_VCCRX1
URC_SQ_VCCRX2
URC_SQ_VCCTX2
URC_SQ_VCCTX3
URC_SQ_VCCRX3
URC_SQ_HDINP0
URC_SQ_VCCIB0
URC_SQ_HDINN0
URC_SQ_HDINN1
URC_SQ_VCCIB1
URC_SQ_HDINP1
URC_SQ_HDINP2
URC_SQ_VCCIB2
URC_SQ_HDINN2
URC_SQ_HDINN3
URC_SQ_VCCIB3
URC_SQ_HDINP3
URC_SQ_VCCP
Function
Ball/Pad
GNDIO2
VCCIO2
GNDIO1
PR11B
PR11A
PT82B
PT82A
PT81B
PT81A
XRES
PR9B
PR9A
-
LatticeECP2/M Family Data Sheet
Bank
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
2
2
2
2
2
1
1
1
1
1
-
-
-
LFE2M70E/SE
RUM0_SPLLC_IN_A/RDQ15
RUM0_SPLLT_IN_A/RDQ15
Dual Function
Pinout Information
VREF2_2
VREF1_2
Differential
C (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
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