LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 41
![FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M20SE-5FN256C
Manufacturer Part Number
LFE2M20SE-5FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20SE-5FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20SE-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-35. Edge Clock, DLL Calibration and DQS Local Bus Distribution
Spans 16 PIOs
Spans 18 PIOs
DQS Input
Note: Bank 8 is not shown.
I/O
I/O
B
a
n
7
B
a
n
6
k
k
DDR_DLL
I/O Bank 5
(Left)
I/O Bank 0
2-38
I/O Bank 4
I/O Bank 1
DDR_DLL
(Right)
LatticeECP2/M Family Data Sheet
I/O
I/O
B
B
a
n
k
2
a
n
k
3
ECLK1
ECLK2
Delayed
DQS
Polarity Control
DQSXFER
DQS Delay
Control Bus
Architecture
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