LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 82
![FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M20SE-5FN256C
Manufacturer Part Number
LFE2M20SE-5FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20SE-5FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20SE-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Timing Diagrams
Figure 3-9. Read/Write Mode (Normal)
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
Figure 3-10. Read/Write Mode with Input and Output Registers
CLKA
DOA (Regs)
WEA
DOA
CSA
ADA
DIA
CLKA
WEA
ADA
CSA
DIA
t
SU
A0
D0
t
t
H
SU
A0
D0
t
H
Mem(n) data from previous read
A1
D1
A1
D1
3-30
output is only updated during a read cycle
A0
t
A0
CO_EBR
t
COO_EBR
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
D0
A1
A1
t
CO_EBR
D0
D1
A0
A0
t
CO_EBR
t
COO_EBR
D1
D0
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