LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 40
![FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M20SE-5FN256C
Manufacturer Part Number
LFE2M20SE-5FN256C
Description
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M20SE-5FN256C
Number Of Macrocells
19000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
140
Data Ram Size
1246208
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M20SE-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 40 of 389
- Download datasheet (5Mb)
Lattice Semiconductor
Figure 2-34. DQS Input Routing for the Bottom Edge of the Device
DLL Calibrated DQS Delay Block
Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at
the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock
(referred to as DQS) is not free-running so this approach cannot be used. The DQS Delay block provides the
required clock alignment for DDR memory interfaces.
The DQS signal (selected PIOs only, as shown in Figure 2-35) feeds from the PAD through a DQS delay element to
a dedicated DQS routing resource. The DQS signal also feeds polarity control logic, which controls the polarity of
the clock to the sync registers in the input register blocks. Figure 2-35 and Figure 2-36 show how the DQS transi-
tion signals are routed to the PIOs.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration
(6-bit bus) signals from two dedicated DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates
DQS delays in its half of the device as shown in Figure 2-35. The DLL loop is compensated for temperature, volt-
age and process variations by the system clock and feedback loop.
DQS
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
2-37
Buffer
Delay
sysIO
LatticeECP2/M Family Data Sheet
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
DQS Pin
Assigned
PADA "T"
PADB "C"
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
Architecture
Related parts for LFE2M20SE-5FN256C
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![LFE2M20SE-5FN484C](/photos/16/14/161499/landingpagelatticeecp2m_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 19K LUTs 304 I/O S-Ser SERDES DSP -5
Manufacturer:
Lattice
Datasheet:
![LFE2M20SE-5FN484I](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFE2M20SE-5FN256I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 256-Pin FBGA
Manufacturer:
Lattice
Datasheet:
![LFE2M20SE-6FN256C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 20KLUTS 140I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
![LFE2M20SE-7FN256C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 20KLUTS 140I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
![LFE2M20SE-7FN484C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 20KLUTS 304I/O 484-BGA
Manufacturer:
Lattice
Datasheet:
![LFE2M20SE-6FN484C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 19KLUTS 484FGPBGA
Manufacturer:
Lattice
Datasheet:
![LFE2M20SE-6F484C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 19K LUTs 304 I/O S-Ser SERD DSP -6
Manufacturer:
Lattice
![LFE2M20SE-7F484C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 19K LUTs 304 I/O S-Ser SERD DSP -7
Manufacturer:
Lattice
![LFE2M20SE-6F256I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERD DSP -6 I
Manufacturer:
Lattice
![LFE2M20SE-6F256C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERD DSP -6
Manufacturer:
Lattice
![LFE2M20SE-5F484C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 19K LUTs 304 I/O S-Ser SERDES DSP -5
Manufacturer:
Lattice
![LFE2M20SE-6F484I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 19K LUTs 304 I/O S-Ser SERD DSP -6 I
Manufacturer:
Lattice