EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 141
EP4CGX75DF27C7N
Manufacturer Part Number
EP4CGX75DF27C7N
Description
Cyclone IV GX
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX75DF27C7N
Number Of Logic Elements/cells
73920
Number Of Labs/clbs
4620
Total Ram Bits
4257792
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
*
Operating Temperature
0°C ~ 85°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX75DF27C7N
Manufacturer:
SONGCHUAN
Quantity:
1 000
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Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Standards Support
LVPECL I/O Support in Cyclone IV Devices
© December 2010 Altera Corporation
f
Figure 6–17
bottom I/O banks.
Figure 6–17. RSDS Interface with Single Resistor Network on the Top and Bottom I/O Banks
Note to
(1) R
The LVPECL I/O standard is a differential interface standard that requires a 2.5-V
V
telecommunications, data communications, and clock distribution. Cyclone IV
devices support the LVPECL input standard at the dedicated clock input pins only.
The LVPECL receiver requires an external 100- termination resistor between the two
signals at the input buffer.
For the LVPECL I/O standard electrical specification, refer to the
Datasheet
AC coupling is required when the LVPECL common mode voltage of the output
buffer is higher than the Cyclone IV devices LVPECL input common mode voltage.
Figure 6–18
receiver are external to the device. DC-coupled LVPECL is supported if the LVPECL
output common mode voltage is in the Cyclone IV devices LVPECL input buffer
specification (refer to
(Note 1)
CCIO.
P
This standard is used in applications involving video graphics,
value is pending characterization.
Figure
RSDS Transmitter
chapter.
Cyclone IV Device
6–17:
Emulated
shows the RSDS interface with a single resistor network on the top and
shows the AC-coupled termination scheme. The 50- resistors used at the
Figure
Single Resistor Network
6–19).
R
P
50 Ω
50 Ω
100 Ω
Cyclone IV Device Handbook, Volume 1
Cyclone IV Device
RSDS Receiver
6–33
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