EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 290
EP4CGX75DF27C7N
Manufacturer Part Number
EP4CGX75DF27C7N
Description
Cyclone IV GX
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX75DF27C7N
Number Of Logic Elements/cells
73920
Number Of Labs/clbs
4620
Total Ram Bits
4257792
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
*
Operating Temperature
0°C ~ 85°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX75DF27C7N
Manufacturer:
SONGCHUAN
Quantity:
1 000
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1–10
Receiver Channel Datapath
Receiver Input Buffer
Cyclone IV Device Handbook, Volume 2
The following sections describe the Cyclone IV GX receiver channel datapath
architecture as shown in
Table 1–2
buffer.
Table 1–2. Electrical Features Supported by the Receiver Input Buffer
The high-speed serial link can be AC- or DC-coupled, depending on the serial
protocol implementation. In an AC-coupled link, the AC-coupling capacitor blocks
the transmitter DC common mode voltage as shown in
and on-chip biasing circuitry automatically restores the common mode voltage. The
biasing circuitry is also enabled by enabling OCT. If you disable the OCT, then you
must externally terminate and bias the receiver. AC-coupled links are required for
PCIe, GbE, Serial RapidIO, SDI, XAUI, SATA, V-by-One and Display Port protocols.
1.4-V PCML
1.5-V PCML
2.5-V PCML
LVPECL
LVDS
Note to
(1) DC coupling is supported for LVDS with lower on-chip common mode voltage of 0.82 V.
■
■
■
■
■
■
■
■
■
■
“Receiver Input Buffer” on page 1–10
“Clock Data Recovery” on page 1–13
“Deserializer” on page 1–14
“Word Aligner” on page 1–15
“Deskew FIFO” on page 1–20
“Rate Match FIFO” on page 1–21
“8B/10B Decoder” on page 1–21
“Byte Deserializer” on page 1–22
“Byte Ordering” on page 1–22
“RX Phase Compensation FIFO” on page 1–23
Table
lists the electrical features supported by the Cyclone IV GX receiver input
1–2:
I/O Standard
Figure 1–3 on page
Programmable Common
Mode Voltage (V)
1–3:
0.82
0.82
0.82
0.82
0.82
Chapter 1: Cyclone IV Transceivers Architecture
Figure
© December 2010 Altera Corporation
1–12. Receiver OCT
Receiver Channel Datapath
AC, DC
Coupling
AC, DC
AC, DC
AC
AC
(1)
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