EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 46

• Manufacturer Part Number: EP4CGX75DF27C7N
• Description: Cyclone IV GX
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX75DF27C7N

• Number Of Logic Elements/cells: 73920
• Number Of Labs/clbs: 4620
• Total Ram Bits: 4257792
• Number Of I /o: 310
• Number Of Gates: -
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: *
• Operating Temperature: 0°C ~ 85°C
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3–10
Figure 3–9. Cyclone IV Devices Simple Dual-Port Timing Waveform
True Dual-Port Mode
Cyclone IV Device Handbook, Volume 1
q (asynch)
wraddress
rdaddress
wrclock
rdclock
wren
data
rden
1
din-1
doutn-1
an-1
Figure 3–9
dual-port mode with unregistered outputs. Registering the outputs of the RAM
simply delays the q output by one clock cycle.
True dual-port mode supports any combination of two-port operations: two reads,
two writes, or one read and one write, at two different clock frequencies.
shows Cyclone IV devices true dual-port memory configuration.
Figure 3–10. Cyclone IV Devices True Dual-Port Memory
Note to
(1) True dual-port memory supports input or output clock mode in addition to the independent clock mode shown.
The widest bit configuration of the M9K blocks in true dual-port mode is 512 × 16-bit
(18-bit with parity).
bn
Figure
an
din
shows the timing waveform for read and write operations in simple
3–10:
doutn
b0
a0
a1
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
clocken_a
rden_a
aclr_a
q_a[]
clock_a
dout0
a2
b1
a3
addressstall_b
address_b[]
byteena_b[]
Chapter 3: Memory Blocks in Cyclone IV Devices
clocken_b
data_b[ ]
(Note 1)
clock_b
wren_b
rden_b
aclr_b
q_b[]
din4
b2
a4
© November 2009 Altera Corporation
din5
a5
b3
a6
din6
Figure 3–10
Memory Modes