EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 329
EP4CGX75DF27C7N
Manufacturer Part Number
EP4CGX75DF27C7N
Description
Cyclone IV GX
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX75DF27C7N
Number Of Logic Elements/cells
73920
Number Of Labs/clbs
4620
Total Ram Bits
4257792
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
*
Operating Temperature
0°C ~ 85°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX75DF27C7N
Manufacturer:
SONGCHUAN
Quantity:
1 000
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Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
© December 2010 Altera Corporation
f
1
For more information about PCIe implementation with hard IP module, refer to the
PCI Express Compiler User
Figure 1–49
Figure 1–49. Transceiver Configuration in PIPE Mode
When configuring the transceiver into PIPE mode using ALTGX megafunction for
PCIe implementation, the PHY-MAC, data link and transaction layers must be
implemented in user logics. The PCIe hard IP block is bypassed in this configuration.
PIPE Interface
The PIPE interface provides a standard interface between the PCIe-compliant PHY
and MAC layer as defined by the version 2.00 of the PIPE Architecture specification
for Gen1 (2.5 Gbps) signaling rate. Any core or IP implementing the PHY MAC, data
link, and transaction layers that supports PIPE 2.00 can be connected to the
Cyclone IV GX transceiver configured in PIPE mode.
ports available from the Cyclone IV GX transceiver configured in PIPE mode and the
corresponding port names in the PIPE 2.00 specification.
Functional Mode
Channel Bonding
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
Data Rate (Gbps)
shows the transceiver configuration in PIPE mode.
Guide.
Automatic Synchronization
State Machine (10-Bit)
PCI Express (PIPE)
Table 1–15
×1, ×2, ×4
Disabled
Disabled
Enabled
Enabled
Enabled
16-Bit
125
2.5
Cyclone IV Device Handbook, Volume 2
lists the PIPE-specific
1–49
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