EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 53

• Manufacturer Part Number: EP4CGX75DF27C7N
• Description: Cyclone IV GX
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX75DF27C7N

• Number Of Logic Elements/cells: 73920
• Number Of Labs/clbs: 4620
• Total Ram Bits: 4257792
• Number Of I /o: 310
• Number Of Gates: -
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: *
• Operating Temperature: 0°C ~ 85°C
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 3: Memory Blocks in Cyclone IV Devices
Design Considerations
Conflict Resolution
© November 2009 Altera Corporation
f
1
Mixed-Port Read-During-Write Mode
This mode applies to a RAM in simple or true dual-port mode, which has one port
reading and the other port writing to the same address location with the same clock.
In this mode, you also have two output choices: Old Data mode or Don't Care mode.
In Old Data mode, a read-during-write operation to different ports causes the RAM
outputs to reflect the old data at that address location. In Don't Care mode, the same
operation results in a “Don't Care” or unknown value on the RAM outputs.
For more information about how to implement the desired behavior, refer to the
Megafunction User
Figure 3–16
behavior for Old Data mode. In Don't Care mode, the old data is replaced with
“Don't Care”.
Figure 3–16. Mixed Port Read-During-Write: Old Data Mode
For mixed-port read-during-write operation with dual clocks, the relationship
between the clocks determines the output behavior of the memory. If you use the
same clock for the two clocks, the output is the old data from the address location.
However, if you use different clocks, the output is unknown during the mixed-port
read-during-write operation. This unknown value may be the old or new data at the
address location, depending on whether the read happens before or after the write.
When you are using M9K memory blocks in true dual-port mode, it is possible to
attempt two write operations to the same memory location (address). Because there is
no conflict resolution circuitry built into M9K memory blocks, this results in
unknown data being written to that location. Therefore, you must implement
conflict-resolution logic external to the M9K memory block.
q_b (asynch)
address_b
address_a
clk_a&b
wren_a
rden_b
data_a
shows a sample functional waveform of mixed port read-during-write
Guide.
A
a (old data)
a
a
B
A
C
B
D
b (old data)
Cyclone IV Device Handbook, Volume 1
E
b
b
D
F
E
RAM
3–17