EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 340

• Manufacturer Part Number: EP4CGX75DF27C7N
• Description: Cyclone IV GX
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX75DF27C7N

• Number Of Logic Elements/cells: 73920
• Number Of Labs/clbs: 4620
• Total Ram Bits: 4257792
• Number Of I /o: 310
• Number Of Gates: -
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: *
• Operating Temperature: 0°C ~ 85°C
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1–60
Cyclone IV Device Handbook, Volume 2
Figure 1–61
Figure 1–61. Transceiver Configuration in Serial RapidIO Mode
Lane Synchronization
In Serial RapidIO mode, the word aligner is compliant to the SRIO Specification 1.3
and is configured in automatic synchronization state machine mode with the
parameter settings as listed in
Table 1–20. Synchronization State Machine Parameters
Number of valid synchronization (/K28.5/) code groups received to achieve
synchronization
Number of erroneous code groups received to lose synchronization
Number of continuous good code groups received to reduce the error count by
one
Note to
(1) The word aligner supports 10-bit pattern lengths in SRIO mode.
Table
Functional Mode
Channel Bonding
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
Data Rate (Gbps)
1–20:
shows the transceiver configuration in Serial RapidIO mode.
Table
Parameter
1–20.
Disabled
62.5/125/
1.25/2.5/
Enabled
Enabled
Chapter 1: Cyclone IV Transceivers Architecture
(Note 1)
16-Bit
156.25
3.125
Automatic Synchronization
State Machine (10-Bit)
Disabled
Enabled
SRIO
×1
© December 2010 Altera Corporation
Disabled
62.5/125/
1.25/2.5/
Disabled
Enabled
156.25
16-Bit
3.125
Transceiver Functional Modes
Value
127
255
3