EP4CGX75DF27C7N Altera, EP4CGX75DF27C7N Datasheet - Page 96

• Manufacturer Part Number: EP4CGX75DF27C7N
• Description: Cyclone IV GX
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX75DF27C7N

• Number Of Logic Elements/cells: 73920
• Number Of Labs/clbs: 4620
• Total Ram Bits: 4257792
• Number Of I /o: 310
• Number Of Gates: -
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: *
• Operating Temperature: 0°C ~ 85°C
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5–34
Figure 5–21. Delay Insertion Using VCO Phase Output and Counter Delay Time
PLL Cascading
Cyclone IV Device Handbook, Volume 1
CLK0
CLK1
CLK2
135
180
225
270
315
45
90
0
1/8 t
1
VCO
You can use the coarse and fine phase shifts to implement clock delays in
Cyclone IV devices.
Cyclone IV devices support dynamic phase shifting of VCO phase taps only. The
phase shift is configurable for any number of times. Each phase shift takes about one
scanclk cycle, allowing you to implement large phase shifts quickly.
Cyclone IV devices allow cascading between general purpose PLLs and multipurpose
PLLs in normal or direct mode through the GCLK network. If your design cascades
PLLs, the source (upstream) PLL must have a low-bandwidth setting, while the
destination (downstream) PLL must have a high-bandwidth setting.
PLL_6 and PLL7 have upstream cascading capability only.
t
d0-1
t
d0-2
t
VCO
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
© December 2010 Altera Corporation
PLL Cascading