KSZ8893MBLI Micrel Inc, KSZ8893MBLI Datasheet - Page 62

2+1 Port 10/100 Switch W/ Tranceivers & Frame Buffers ( )

KSZ8893MBLI

Manufacturer Part Number
KSZ8893MBLI
Description
2+1 Port 10/100 Switch W/ Tranceivers & Frame Buffers ( )
Manufacturer
Micrel Inc
Datasheet

Specifications of KSZ8893MBLI

Controller Type
Ethernet Switch Controller
Interface
MII, RMII, SNI
Voltage - Supply
3.1 V ~ 3.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFBGA
Number Of Primary Switch Ports
3
Operating Supply Voltage (typ)
3.3V
Fiber Support
Yes
Integrated Led Drivers
Yes
Power Supply Type
Analog/Digital
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.5V
Operating Supply Voltage (min)
3.1V
Operating Temperature Classification
Industrial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Not Compliant, Lead free / RoHS Compliant
Other names
576-3575

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8893MBLI
Manufacturer:
Micrel
Quantity:
2 022
Part Number:
KSZ8893MBLI
Manufacturer:
Micrel Inc
Quantity:
10 000
Part Number:
KSZ8893MBLI
0
Register 1 (0x01): Chip ID1 / Start Switch
Register 2 (0x02): Global Control 0
Bit
7-4
3-1
0
Bit
7
6-4
3
2
1
0
February 2010
Name
Chip ID
Revision ID
Start Switch
Name
New Back-off
Enable
Reserved
Pass Flow
Control Packet
Reserved
Reserved
Link Change
Age
R/W
RO
RO
RW
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
0x2 is assigned to M series. (93M)
Revision ID
= 1, start the chip when external pins
Note: In (PS1, PS0) = (0, 0) mode, the chip will start
automatically after trying to read the external
EEPROM. If EEPROM does not exist, the chip will
use pin strapping and default values for all internal
registers. If EEPROM is present, the contents in the
EEPROM will be checked. The switch will check: (1)
Register 0 = 0x88, (2) Register 1 bits [7:4] = 0x2. If
this check is OK, the contents in the EEPROM will
override chip registers’ default values.
= 0, chip will not start when external pins
Description
New back-off algorithm designed for UNH
Reserved
Do not change the default value.
= 1, switch will not filter 802.1x “flow control” packets
Reserved
Do not change the default value.
Reserved
Do not change the default value.
= 1, link change from “link” to “no link” will cause fast
aging (<800us) to age address table faster. After an
age cycle is complete, the age logic will return to
normal aging (about 200 sec).
Note: If any port is unplugged, all addresses will be
automatically aged out.
(PS1, PS0) = (0,1) or (1,0) or (1,1).
1 = Enable
0 = Disable
(PS1, PS0) = (0,1) or (1,0) or (1,1).
62
Default
0x2
-
-
Default
0
100
0
1
0
0
M9999-021110-1.6

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