KSZ8893MBLI Micrel Inc, KSZ8893MBLI Datasheet - Page 9

• Manufacturer Part Number: KSZ8893MBLI
• Description: 2+1 Port 10/100 Switch W/ Tranceivers & Frame Buffers ( )
• Manufacturer: Micrel Inc

Specifications of KSZ8893MBLI

• Controller Type: Ethernet Switch Controller
• Interface: MII, RMII, SNI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFBGA
• Number Of Primary Switch Ports: 3
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant, Lead free / RoHS Compliant
• Other names: 576-3575

Micrel, Inc.
KSZ8893MQL/MBL
List of Tables
Table 1. FX and TX Mode Selection.................................................................................................................................................. 29
Table 2. MDI/MDI-X Pin Definitions................................................................................................................................................... 30
Table 3. MII Signals ........................................................................................................................................................................... 39
Table 4: RMII Signal Description ...................................................................................................................................................... 40
Table 5: RMII Signal Connections .................................................................................................................................................... 41
Table 6. SNI Signals .......................................................................................................................................................................... 41
Table 7. MII Management Interface Frame Format .......................................................................................................................... 42
Table 8. Serial Management Interface (SMI) Frame Format............................................................................................................ 43
Table 9: Spanning Tree States ......................................................................................................................................................... 44
Table 10. Special Tagging Mode Format.......................................................................................................................................... 45
Table 11. STPID Egress Rules (Processor to Switch Port 3).......................................................................................................... 45
Table 12. STPID Egress Rules (Switch Port 3 to Processor).......................................................................................................... 46
Table 13. FID+DA Lookup in VLAN Mode ........................................................................................................................................ 47
Table 14. FID+SA Lookup in VLAN Mode ........................................................................................................................................ 48
Table 15. KSZ8893MQL/MBL SPI Connections ............................................................................................................................... 52
Table 16. Format of Static MAC Table (8 Entries) ........................................................................................................................... 93
Table 17. Format of Static VLAN Table (16 Entries)........................................................................................................................ 94
Table 18. Format of Dynamic MAC Address Table (1K Entries)..................................................................................................... 95
Table 19. Format of “Per Port” MIB Counters ................................................................................................................................. 96
Table 20. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets ........................................................................................... 97
Table 21. Format of “All Port Dropped Packet” MIB Counters....................................................................................................... 97
Table 22. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets .............................................................................. 97
Table 23. EEPROM Timing Parameters.......................................................................................................................................... 102
Table 24. SNI Timing Parameters ................................................................................................................................................... 103
Table 25. MAC Mode MII Timing Parameters................................................................................................................................. 104
Table 26. PHY Mode MII Timing Parameters.................................................................................................................................. 105
Table 27: RMII Timing Parameters ................................................................................................................................................. 106
Table 28. I2C Timing Parameters..................................................................................................................................................... 107
Table 29. SPI Input Timing Parameters.......................................................................................................................................... 108
Table 30. SPI Output Timing Parameters....................................................................................................................................... 109
Table 31: Auto-Negotiation Timing Parameters ............................................................................................................................ 110
Table 32. Reset Timing Parameters ............................................................................................................................................... 111
Table 33. Transformer Selection Criteria....................................................................................................................................... 113
Table 34. Qualified Single Port Magnetics..................................................................................................................................... 113
Table 35. Typical Reference Crystal Characteristics .................................................................................................................... 113
February 2010
9
M9999-021110-1.6