LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 118

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.7 (06-29-10)
9.5.1
FIELD
FIELD
15:0
7:0
The Filter i Offset register defines the offset in the frame’s destination address field from which the
frames are examined by Filter i.
The Filter i CRC-16 register contains the CRC-16 result of the frame that should pass Filter i.
Table 9.6
Magic Packet Detection
Setting the Magic Packet Enable bit (MPEN) in the
(HMAC_WUCSR)
data reception is disabled, and detection logic within the Host MAC examines received data for a Magic
Packet. The LAN9312 can be programmed to notify the host of the “Magic Packet” detection with the
assertion of the host interrupt (IRQ) or power management event signal (PME). Upon detection, the
Magic Packet Received bit (MPR) in the HMAC_WUCSR register is set. When the host clears the
MPEN bit, the Host MAC will resume normal receive operation. Please refer to
MAC Wake-up Control and Status Register (HMAC_WUCSR)," on page 284
on this register.
In Magic Packet mode, the Host MAC constantly monitors each frame addressed to the node for a
specific Magic Packet pattern. Only packets matching the Host MAC address or broadcast address are
checked for the Magic Packet requirements. Once the address requirement has been met, the Host
MAC checks the received frame for the pattern 48’hFF_FF_FF_FF_FF_FF after the destination and
source address field. The Host MAC then looks in the frame for 16 repetitions of the Host MAC address
without any breaks or interruptions. In case of a break in the 16 address repetitions, the Host MAC
again scans for the 48'hFF_FF_FF_FF_FF_FF pattern in the incoming frame. The 16 repetitions may
be anywhere in the frame but must be preceded by the synchronization stream. The device will also
accept a multicast frame, as long as it detects the 16 duplications of the Host MAC address.
For example, if the Host MAC address is 00h 11h 22h 33h 44h 55h, then the MAC scans for the
following data sequence in an Ethernet frame:
DESCRIPTION
Pattern Offset: The offset of the first byte in the frame on which CRC is checked for wake-up frame
recognition. The minimum value of this field must be 12 since there should be no CRC check for
the destination address and the source address fields. The Host MAC checks the first offset byte
of the frame for CRC and checks to determine whether the frame is a wake-up frame. Offset 0 is
the first byte of the incoming frame's destination address.
DESCRIPTION
Pattern CRC-16: This field contains the 16-bit CRC value from the pattern and the byte mask
programmed to the wake-up filter register function. This value is compared against the CRC
calculated on the incoming frame, and a match indicates the reception of a wakeup frame.
describes the Filter i CRC-16 bit fields.
places the Host MAC in the “Magic Packet” detection mode. In this mode, normal
Table 9.6 Filter i CRC-16 Bit Definitions
Table 9.5 Filter i Offset Bit Definitions
FILTER i OFFSET DESCRIPTION
FILTER i CRC-16 DESCRIPTION
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Table 9.5
DATASHEET
118
describes the Filter i Offset bit fields.
Host MAC Wake-up Control and Status Register
for additional information
Section 14.3.12, "Host
SMSC LAN9312
Datasheet