LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 263

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.2.9.4
31:18
13:11
BITS
17
16
15
14
10
9
RESERVED
Energy-Detect Status Port 2 (ED_STS2)
This bit indicates an energy detect event occurred on the Port 2 PHY.
In order to clear this bit, it is required that the event in the PHY be cleared
as well. The event sources are described in
Management," on page
Energy-Detect Status Port 1 (ED_STS1)
This bit indicates an energy detect event occurred on the Port 1 PHY.
In order to clear this bit, it is required that the event in the PHY be cleared
as well. The event sources are described in
Management," on page
Energy-Detect Enable Port 2 (ED_EN2)
When set, the PME signal (if enabled via the PME_EN bit) will be asserted
in accordance with the PME_IND bit upon an energy-detect event from Port
2. When set, the PME_INT bit in the
also be asserted upon an energy-detect event from Port 2, regardless of the
setting of the PME_EN bit.
Note:
Energy-Detect Enable Port 1 (ED_EN1)
When set, the PME signal (if enabled via the PME_EN bit) will be asserted
in accordance with the PME_IND bit upon an energy-detect event from Port
1. When set, the PME_INT bit in the
also be asserted upon an energy-detect event from Port 1, regardless of the
setting of the PME_EN bit.
Note:
RESERVED
Virtual PHY Reset (VPHY_RST)
Writing a 1 to this bit resets the Virtual PHY. When the Virtual PHY is
released from reset, this bit is automatically cleared. All writes to this bit are
ignored while this bit is high.
Wake-On-LAN Enable (WOL_EN)
When set, the PME signal (if enabled via the PME_EN bit) will be asserted
in accordance with the PME_IND bit upon a WOL event. When set, the
PME_INT bit in the
upon a WOL event, regardless of the setting of the PME_EN bit.
Power Management Control Register (PMT_CTRL)
This read-write register controls the power management features and the PME pin of the LAN9312.
The ready state of the LAN9312 can be determined via the Device Ready (READY) bit of this register.
Refer to
Note: This register is one of only four registers (the others are HW_CFG, BYTE_TEST, and
The EDPWRDOWN bit of the
Register (PHY_MODE_CONTROL_STATUS_x)
must also be set to enable the energy detect feature.
The EDPWRDOWN bit in the
Register (PHY_MODE_CONTROL_STATUS_x)
must also be set to enable the energy detect feature.
RESET_CTL) which can be polled while the LAN9312 is in the reset or not ready state (READY
bit is cleared).
Offset:
Section 4.3, "Power Management," on page 46
Interrupt Status Register (INT_STS)
46.
46.
084h
DESCRIPTION
Interrupt Status Register (INT_STS)
Interrupt Status Register (INT_STS)
DATASHEET
Port x PHY Mode Control/Status
Port x PHY Mode Control/Status
263
Section 4.3, "Power
Section 4.3, "Power
Size:
will also be asserted
of the Port 2 PHY
of the Port 1 PHY
for additional information.
32 bits
will
will
R/WC
R/WC
TYPE
R/W
R/W
R/W
R/W
RO
RO
SC
Revision 1.7 (06-29-10)
DEFAULT
0b
0b
0b
0b
0b
0b
-
-