LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 139

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
10.2.2
Figure 10.1
I
The I
transmission and reception, acknowledge generation and reception) for connection to I
and consists of a data wire (EE_SDA) and a serial clock (EE_SCL). The serial clock is driven by the
master, while the data wire is bi-directional. Both signals are open-drain and require external pull-up
resistors.
The serial clock is also used as an input as it can be held low by the slave device in order to wait-
state the data cycle. Once the slave has data available or is ready to receive, it will release the clock.
Assuming the masters clock low time is also expired, the clock will rise and the cycle will continue. In
the event that the slave device holds the clock low for more than 30mS, the current command
sequence is aborted and the EPC_TIMEOUT bit in the
set. Both the clock and data signals have Schmitt trigger inputs and digital input filters. The digital filters
reject pulses that are less than 100nS.
Note: Since the I
Based on the configuration strap eeprom_size_strap, various sized I
varying size ranges are supported by additional bits in the address field (EPC_ADDRESS) of the
EEPROM Command Register
address bits, while the smaller EEPROMs treat the upper address bits as don’t cares. The EEPROM
2
C EEPROM
2
EPC_BUSY = 0
C master implements a low level serial interface (start and stop condition generation, data bit
supported.
illustrates the process required to perform an EEPROM read or write operation.
EEPROM Write
2
C master is designed to access EEPROM only, multi-master arbitration is not
Figure 10.1 EEPROM Access Flow Diagram
E2P_DATA
E2P_CMD
E2P_CMD
Register
Register
Register
Write
Write
Read
Idle
(E2P_CMD). Within each size range, the largest EEPROM uses all the
DATASHEET
139
EEPROM Command Register (E2P_CMD)
EEPROM Read
E2P_DATA
E2P_CMD
E2P_CMD
Register
Register
Register
Write
Read
Read
Idle
2
C EEPROMs are supported. The
EPC_BUSY = 0
Revision 1.7 (06-29-10)
2
C EEPROMs,
is