LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 143

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
10.2.2.5
A
C
K
D
7
D
6
Data Byte
D
5
Data Cycle
D
4
Sequential reads are used by the EEPROM Loader. Refer to
additional information.
For a register level description of a read operation, refer to
Operation," on page
I
Following the device addressing, a data byte may be written to the EEPROM by outputting the data
after receiving the acknowledge from the EEPROM. The data byte is acknowledged by the EEPROM
slave and the I
send an acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit in the
Command Register (E2P_CMD)
Following the data byte write cycle, the I
write is finished. A start condition is sent followed by a control byte with a control code of 1010b,
chip/block select bits low, and the R/~W bit low. If the EEPROM is finished with the byte write, it will
respond with an acknowledge. Otherwise, it will respond with a no-acknowledge and the I
will repeat the poll. If the acknowledge does not occur within 30mS, a time-out occurs. Once the I
master receives the acknowledge, it concludes by sending a start condition, followed by a stop
condition, which will place the EEPROM into standby.
Figure 10.4
D
3
For a register level description of a write operation, refer to
Operation," on page
2
C EEPROM Byte Writes
D
2
D
1
D
0
A
C
K
illustrates typical I
P
2
S 1 0 1 0
C master finishes the write cycle with a stop condition. If the EEPROM slave fails to
138.
138.
Control Byte
Poll Cycle
Chip / Block
Select Bits
Figure 10.6 I
0 0 0
2
C EEPROM byte write.
is set.
DATASHEET
0
R/~W
2
C
A
K
C EEPROM Byte Write
2
S 1 0 1 0
C master will poll the EEPROM to determine when the byte
143
Control Byte
Poll Cycle
Chip / Block
Select Bits
0 0 0
0
R/~W
Section 10.2.4, "EEPROM Loader"
Section 10.2.1, "EEPROM Controller
Section 10.2.1, "EEPROM Controller
A
C
K
...
S 1 0 1 0
Control Byte
Poll Cycle
Chip / Block
Select Bits
Revision 1.7 (06-29-10)
0 0 0
2
0
Conclude
R/~W
EEPROM
C master
A
C
K
S P
for
2
C