LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 227

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
BITS
3
2
1
0
1588 Port 0(Host MAC) TX Interrupt (1588_MII_TX_INT)
This interrupt indicates that a packet from the Host MAC to the switch fabric
matches the configured PTP packet and the 1588 clock was captured.
Note:
1588 GPIO9 Interrupt (1588_GPIO9_INT)
This interrupt indicates that an event on GPIO9 occurred and the 1588 clock
was captured. These interrupts are configured through the
I/O Configuration Register (GPIO_CFG)
Note:
1588 GPIO8 Interrupt (1588_GPIO8_INT)
This interrupt indicates that an event on GPIO8 occurred and the 1588 clock
was captured. These interrupts are configured through the
I/O Configuration Register (GPIO_CFG)
Note:
1588 Timer Interrupt (1588_TIMER_INT)
This interrupt indicates that the 1588 clock equaled or passed the Clock
Target value in the
(1588_CLOCK_TARGET_HI)
(1588_CLOCK_TARGET_LO).
Note:
For Port 0, receive is defined as data from the switch fabric, while
transmit is to the switch fabric.
As 1588 capture inputs, GPIO inputs are edge sensitive and must
be active for greater than 40 nS to be recognized as interrupt
inputs.
As 1588 capture inputs, GPIO inputs are edge sensitive and must
be active for greater than 40 nS to be recognized as interrupt
inputs.
This bit is also cleared by an active edge on GPIO[9:8] if enabled.
For the clear function, GPIO inputs are edge sensitive and must be
active for greater than 40 nS to be recognized as a clear input.
Refer to
additional information.
Section 13.2, "GPIO Operation," on page 162
1588 Clock Target High-DWORD Register
and
DESCRIPTION
1588 Clock Target Low-DWORD Register
DATASHEET
register.
register.
227
General Purpose
General Purpose
for
TYPE
R/WC
R/WC
R/WC
R/WC
Revision 1.7 (06-29-10)
DEFAULT
0b
0b
0b
0b