LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 82

• Manufacturer Part Number: LAN9312-NZW
• Description: Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9312-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 186 mA, 295 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7 Ethernet PHYs
Revision 1.7 (06-29-10)
7.1
7.1.1
PHY_ADDR_SEL_STRAP
The LAN9312 contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs
are identical in functionality and each connect their corresponding Ethernet signal pins to the switch
fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII
interface. The Virtual PHY provides the virtual functionality of a PHY and allows connection of the Host
MAC to port 0 of the switch fabric as if it was connected to a single port PHY. All PHYs comply with
the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full/half duplex 100
Mbps (100BASE-TX) or 10Mbps (10BASE-T) Ethernet operation. All PHY registers follow the IEEE
802.3 (clause 22.2.4) specified MII management register set and can be configured indirectly via the
Host MAC, or directly via the memory mapped Virtual PHY registers. Refer to
PHY Control and Status Registers"
The LAN9312 Ethernet PHYs are discussed in detail in the following sections:
PHY Addressing
Each individual PHY is assigned a unique default PHY address via the phy_addr_sel_strap
configuration strap as shown in
be changed via the
(PHY_SPECIAL_MODES_x). For proper operation, all LAN9312 PHY addresses must be unique. No
check is performed to assure each PHY is set to a different address. Configuration strap values are
latched upon the de-assertion of a chip-level reset as described in
Straps," on page
Functional Overview
0
1
Section 7.2, "Port 1 & 2 PHYs," on page 83
Section 7.3, "Virtual PHY," on page 96
40.
VIRTUAL PHY DEFAULT
Table 7.1 Default PHY Serial MII Addressing
ADDRESS VALUE
PHY Address (PHYADD)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
0
1
Table
DATASHEET
for details on the Ethernet PHY registers.
7.1. In addition, the Port 1 PHY and Port 2 PHY addresses can
82
PORT 1 PHY DEFAULT
field in the
ADDRESS VALUE
1
2
Port x PHY Special Modes Register
Section 4.2.4, "Configuration
PORT 2 PHY DEFAULT
ADDRESS VALUE
Section 14.4, "Ethernet
2
3
SMSC LAN9312
Datasheet