LAN9312-NZW SMSC, LAN9312-NZW Datasheet - Page 62

Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch

LAN9312-NZW

Manufacturer Part Number
LAN9312-NZW
Description
Ethernet ICs Hi Per 2 Port 10/100 Ethernet Switch
Manufacturer
SMSC
Type
Two Port Managed Ethernet Switchr
Datasheet

Specifications of LAN9312-NZW

Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Switches
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 Mbps, 100 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Supply Current (max)
186 mA, 295 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
Standard
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Quantity:
10 000
Revision 1.7 (06-29-10)
6.3.2
6.3.2.1
Transmit MAC
The transmit MAC generates an Ethernet MAC frame from TX FIFO data. This includes generating the
preamble and SFD, calculating and appending the frame checksum value, optionally padding
undersize packets to meet the minimum packet requirement size (64 bytes), and maintaining a
standard inter-frame gap time during transmit.
The transmit MAC can operate at 10/100Mbps, half- or full-duplex, and with or without flow control
depending on the state of the transmission. In half-duplex mode the transmit MAC meets CSMA/CD
IEEE 802.3 requirements. The transmit MAC will re-transmit if collisions occur during the first 64 bytes
(normal collisions), or will discard the packet if collisions occur after the first 64 bytes (late collisions).
The transmit MAC follows the standard truncated binary exponential back-off algorithm, collision and
jamming procedures.
The transmit MAC pre-pends the standard preamble and SFD to every packet from the FIFO. The
transmit MAC also follows as default, the standard Inter-Frame Gap (IFG). The default IFG is 96 bit
times and can be adjusted via the IFG Config field of the
(MAC_TX_CFG_x).
Packet padding and cyclic redundant code (FCS) calculation may be optionally performed by the
transmit MAC. The auto-padding process automatically adds enough zeros to packets shorter than 64
bytes. The auto-padding and FCS generation is controlled via the TX Pad Enable bit of the
Transmit Configuration Register
The transmit FIFO acts as a temporary buffer between the transmit MAC and the switch engine. The
FIFO logic manages the re-transmission for normal collision conditions or discards the frames for late
or excessive collisions.
When in full-duplex mode, the transmit MAC uses the flow-control algorithm specified in IEEE 802.3.
MAC pause frames are used primarily for flow control packets, which pass signalling information
between stations. MAC pause frames have a unique type of 8808h, and a pause op-code of 0001h.
The MAC pause frame contains the pause value in the data field. The flow control manager will auto-
adapt the procedure based on traffic volume and speed to avoid packet loss and unnecessary pause
periods.
When in half-duplex mode, the MAC uses a back pressure algorithm. The back pressure algorithm is
based on a forced collision and an aggressive back-off algorithm.
Transmit Counters
The transmit MAC gathers statistics on each packet and increments the related counter registers. The
following transmit counters are supported for each switch fabric port. Refer to
Accessible Switch Control and Status Registers,” on page 307
Section 14.5.2.42
Total packets deferred
Total pause packets
Total OK packets
Total packets 64 bytes in size
Total packets 65 through 127 bytes in size
Total packets 128 through 255 bytes in size
Total packets 256 through 511 bytes in size
Total packets 512 through 1023 bytes in size
Total packets 1024 through maximum bytes in size
Total undersized packets
Total bytes transmitted from all packets
Total broadcast packets
for detailed descriptions of these counters.
(Section 14.5.2.27, on page
(Section 14.5.2.26, on page
(Section 14.5.2.25, on page
(Section 14.5.2.36, on page
(Section 14.5.2.34, on page
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
(MAC_TX_CFG_x).
(Section 14.5.2.28, on page
DATASHEET
62
(Section 14.5.2.35, on page
(Section 14.5.2.29, on page
(Section 14.5.2.31, on page
(Section 14.5.2.30, on page
(Section 14.5.2.32, on page
348)
347)
346)
(Section 14.5.2.33, on page
357)
Port x MAC Transmit Configuration Register
355)
349)
and
356)
Section 14.5.2.25
350)
352)
351)
353)
Table 14.12, “Indirectly
354)
SMSC LAN9312
Port x MAC
Datasheet
through

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