XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 107
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
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X-Ref Target - Figure 3-13
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Matches
1
IBUFG
DCM Driving PLL
2
3
4
5
In some cases precise alignment will not occur because of the difference in loading between
the input capacitance of the external component and the feedback path capacitance of the
FPGA. For example, the external components can have an input capacitance on 1 pF to
4 pF while the FPGA has an input capacitance of around 8 pF. There is a difference in the
signal slope, which is basically skew. Designers need to be aware of this effect to ensure
timing.
The DCM provides an excellent method for generating precision phase-shifted clocks.
However, the DCM cannot reduce the jitter on the reference clock. The PLL can be used to
reduce the output jitter of one DCM clock output. This configuration is shown in
Figure
PLL). The associated waveforms are shown to the right of the block diagram. When the
output of the DCM is used to drive the PLL directly, both DCM and PLL must reside within
the same CMT block. This is the preferred implementation since it produces a minimal
amount of noise on the local, dedicated route. However, a connection can also be made by
connecting the DCM to a BUFG and then to the CLKIN input of a PLL.
CLKIN
CLKFBIN
RST
CLKIN1
CLKFBIN
RST
DCM
PLL
3-13. The PLL is configured to not introduce any phase shift (zero delay through the
CLKFBOUT
CLKFX180
CLK2X180
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLK180
CLK270
CLKDV
Figure 3-13: DCM Driving a PLL
CLKFX
CLK2X
CLK90
CLK0
www.xilinx.com
BUFG
BUFG
6
To Logic, etc.
1
2
3
4
5
6
PLL Use Models
ug190_3_13_092107
107
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