XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 162
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XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
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- XC5VLX30-1FFG324C PDF datasheet #3
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Chapter 4: Block RAM
Table 4-21: Block RAM ECC Port Names and Descriptions
162
Notes:
1. Hamming code implemented in the block RAM ECC logic detects one of three conditions: no detectable error, single-bit error
DI[63:0]
DIP[7:0]
WRADDR[8:0]
RDADDR[8:0]
WREN
RDEN
SSR
WRCLK
RDCLK
DO[63:0]
DOP[7:0]
SBITERR
DBITERR
ECCPARITY[7:0]
detected and corrected on DO (but not corrected in the memory), and double-bit error detected without correction. SBITERR and
DBITERR indicate these three conditions.
Port Name
(1)
(1)
Block RAM and FIFO ECC Port Descriptions
Direction
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Table 4-21
Data input bus.
Data input parity bus. Used in decode-only mode to input the precalculated ECC
parity bits.
Write address bus.
Read address bus.
Write enable. When WREN = 1, data will be written into memory. When WREN = 0,
write is disabled
Read enable. When RDEN = 1, data will be read from memory. When RDEN = 0, read
is disabled.
Not supported when using the block RAM ECC primitive. Always connect to GND.
Clock for write operations.
Clock for read operations.
Data output bus.
Data output parity bus. Used in encode-only mode to output the stored ECC parity
bits.
Single-bit error status.
Double-bit error status.
ECC encoder output bus.
lists and describes the block RAM ECC I/O port names.
www.xilinx.com
Signal Description
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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