XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 116
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
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- XC5VLX30-1FFG324C PDF datasheet #3
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Chapter 4: Block RAM
116
X-Ref Target - Figure 4-1
Table 4-2: True Dual-Port Names and Descriptions
DI[A|B]
DIP[A|B]
ADDR[A|B]
WE[A|B]
EN[A|B]
SSR[A|B]
CLK[A|B]
DO[A|B]
DOP[A|B]
REGCE[A|B]
CASCADEINLAT[A|B]
Port Name
(1)
(1)
CASCADEOUTREGA
Figure 4-1: True Dual-Port Data Flows
CASCADEOUTLATA
www.xilinx.com
CASCADEINREGA
CASCADEINLATA
DIA
DIPA
ADDRA
WEA
ENA
SSRA
REGCEA
DIB
DIPB
ADDRB
WEB
ENB
SSRB
REGCEB
Data Input Bus
Data Input Parity Bus, can be used for additional data inputs
Address Bus
Byte-wide Write Enable
When inactive no data is written to the block RAM and the
output bus remains in its previous state
Synchronous Set/Reset for either latch or register modes
Clock Input
Data Output Bus
Data Output Parity Bus, can be used for additional data
outputs
Output Register Enable
Cascade input pin for 64K x 1 mode when optional output
registers are not enabled
CLKA
CLKB
36-Kbit Block RAM
Memory
Port A
Port B
36 Kb
Array
CASCADEOUTLATB
CASCADEOUTREGB
CASCADEINLATB
CASCADEINREGB
DOPB
DOPA
DOB
DOA
Description
ug0190_4_01_032106
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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