XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 379
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Timing Characteristics of 8:1 DDR Serialization
Figure 8-18
example, a second OSERDES is required to achieve an 8:1 serialization. The two OSERDES
are connected and configured using the methods described in
page
remaining two bits are connected to D3–D4 of the slave OSERDES.
X-Ref Target - Figure 8-18
Clock Event 1
On the rising edge of CLKDIV, the word ABCDEFGH is driven from the FPGA logic to the
D1–D6 inputs of the master OSERDES and D3–D4 of the slave OSERDES (after some
propagation delay).
Clock Event 2
On the rising edge of CLKDIV, the word ABCDEFGH is sampled into the master and slave
OSERDES from the D1–D6 and D3–D4 inputs, respectively.
Clock Event 3
The data bit A appears at OQ four CLK cycles after ABCDEFGH is sampled into the
OSERDES. This latency is consistent with the
OSERDES latency of four CLK cycles.
Master.D1
Master.D2
Master.D3
Master.D4
Master.D5
Master.D6
Slave.D3
Slave.D4
375. Six of the eight bits are connected to D1–D6 of the master OSERDES while the
CLKDIV
CLK
OQ
Figure 8-18: OSERDES Data Flow and Latency in 8:1 DDR Mode
illustrates the timing of an 8:1 DDR data serialization. In contrast to the 2:1 SDR
Event 1
Clock
www.xilinx.com
Output Parallel-to-Serial Logic Resources (OSERDES)
G
A
B
C
D
E
F
H
Event 2
Clock
Table 8-10
M
N
O
K
L
P
J
I
listing of a 8:1 DDR mode
Event 3
Clock
OSERDES Width Expansion,
A B C D E F G H I
UG190_8_18_100307
Event 4
Clock
379
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