XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 37
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
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- Download datasheet (14Mb)
X-Ref Target - Figure 1-16
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
CE
I0
I1
O
S
1
at I0
T
BCCKO_O
BUFGMUX_CTRL with a Clock Enable
A BUFGMUX_CTRL with a clock enable BUFGCTRL configuration allows the user to
choose between the incoming clock inputs. If needed, the clock enable is used to disable
the output.
shows the timing diagram.
X-Ref Target - Figure 1-15
In
•
•
•
•
Figure 1-16: BUFGMUX_CTRL with a CE Timing Diagram
Figure
At time event 1, output O uses input I0.
Before time event 2, S is asserted High.
At time T
to Low transition of I0 followed by a High to Low transition of I1 is completed.
At time T
switched Low and kept at Low after a High to Low transition of I1 is completed.
1-16:
CE
I1
I0
S
Figure 1-15
BCCKO_O
BCCCK_CE
Figure 1-15: BUFGMUX_CTRL with a CE and BUFGCTRL
BUFGMUX_CTRL+CE
2
Design Example
Begin I1
, after time event 2, output O uses input I1. This occurs after a High
, before time event 3, CE is asserted Low. The clock output is
illustrates the BUFGCTRL usage design example and
T
BCCKO_O
www.xilinx.com
O
CE
S
GND
GND
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
Global Clocking Resources
Clock Off
UG190_1_15_052009
3
T
BCCCK_CE
Figure 1-16
ug190_1_16_040907
O
37
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