XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 62
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XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 62 of 385
- Download datasheet (14Mb)
Chapter 2: Clock Management Technology
Table 2-6: DCM Attributes (Continued)
62
CLKOUT_PHASE_SHIFT
DESKEW_ADJUST
DFS_FREQUENCY_MODE
DLL_FREQUENCY_MODE
DUTY_CYCLE_CORRECTION
DCM_PERFORMANCE_MODE
FACTORY_JF
PHASE_SHIFT
STARTUP_WAIT
DCM Attribute Name
This attribute specifies the phase-
shift mode.
This affects the amount of delay in
the feedback path, and should be
used for source-synchronous
interfaces.
This specifies the frequency mode of
the frequency synthesizer.
This specifies the frequency mode of
the DLL.
This controls the DCM 1X outputs
(CLK0, CLK90, CLK180, and
CLK270), to exhibit a 50/50 duty
cycle. Leave this attribute set at the
default value.
Allows selection between maximum
frequency/ minimum jitter, and low
frequency/maximum phase-shift
range
DLL_FREQUENCY_MODE=LOW
default (0x
DLL_FREQUENCY_MODE=HIGH
default (0x
This specifies the phase-shift
numerator. The value range
depends on
CLKOUT_PHASE_SHIFT and clock
frequency.
When this attribute is set to TRUE,
the configuration startup sequence
waits in the specified cycle until the
DCM locks.
F0F0
F0F0)
Description
).
.
www.xilinx.com
String: NONE or FIXED or
VARIABLE_POSITIVE or
VARIABLE_CENTER or
DIRECT
String:
SYSTEM_SYNCHRONOUS
or
SOURCE_SYNCHRONOUS
String: LOW or HIGH
String: LOW or HIGH
Boolean: TRUE or FALSE
String: MAX_SPEED or
MAX_RANGE
BIT_VECTOR
Integer: –255 to 1023
Boolean: FALSE or TRUE
Values
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
NONE
SYSTEM_
SYNCHRONOUS
LOW
LOW
TRUE
MAX_SPEED
0xF0F0
0
FALSE
Default Value
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