XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 168
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XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
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Chapter 4: Block RAM
168
ECC Timing Characteristics
Standard ECC Write Timing
Standard ECC Read Timing
The various ECC timing parameters are also shown in
Since write clock and read clock are independent of each other, all write timing in
Figure 4-31
RDCLK.
•
•
•
•
•
•
DO_REG = 0
DO_REG = 1
At time TRCCK_EN, before time T1W, write enable becomes valid at the WREN input
of the block RAM.
At time TRCCK_ADDR, before time T1W, write address a becomes valid at the
WRADDR[8:0] inputs of the block RAM. WRADDR input is not needed for FIFO.
At time TRDCK_DI_ECC (standard ECC), before time T1W, write data A (hex)
becomes valid at the DI[63:0] inputs of the block RAM.
At time TRCKO_ECC_PARITY (standard ECC), after time T1W, ECC parity data PA
(hex) becomes valid at the ECCPARITY[7:0] output pins of the block RAM.
At time TRCCK_EN, before time T1R, read enable becomes valid at the RDEN input
of the block RAM.
At time TRCCK_ADDR, before time T1R, write address a becomes valid at the
RDADDR[8:0] inputs of the block RAM. RDADDR input is not needed for FIFO.
•
•
•
•
•
•
•
•
At time TRCKO_DO (latch mode), after time T1R, data A (hex) becomes valid at
the DO[63:0] output pins of the block RAM.
At time TRCKO_DOP (latch mode), after time T1R, data PA (hex) becomes valid
at the DOP[7:0] output pins of the block RAM.
At time TRCKO_ECC_SBITERR (latch mode), after time T1R, SBITERR is asserted
if single-bit error is detected and corrected on data set A.
At time TRCKO_ECC_DBITERR (latch mode), after time T2R, DBITERR is
asserted if double-bit error is detected on data set B.
At time TRCKO_DO (register mode), after time T2R, data A (hex) becomes valid
at the DO[63:0] output pins of the block RAM.
At time TRCKO_DOP (register mode), after time T2R, data PA (hex) becomes
valid at the DOP[7:0] output pins of the block RAM.
At time TRCKO_ECCR_SBITERR (register mode), after time T2R, SBITERR is
asserted if single-bit error is detected and corrected on data set A.
At time TRCKO_ECCR_DBITERR (register mode), after time T3R, DBITERR is
asserted if double-bit error is detected on data set B.
is referenced to WRCLK. All read timing in
www.xilinx.com
(Figure
(Figure
4-31)
4-32)
Figure 4-31
Figure 4-32
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
and
is referenced to
Figure
4-32.
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