XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 380
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XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
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Chapter 8: Advanced SelectIO Logic Resources
380
Timing Characteristics of 4:1 DDR 3-State Controller Serialization
The second word IJKLMNOP is sampled into the master and slave OSERDES from the D1–
D6 and D3–D4 inputs, respectively.
Clock Event 4
Between Clock Events 3 and 4, the entire word ABCDEFGH is transmitted serially on OQ,
a total of eight bits transmitted in one CLKDIV cycle.
The data bit I appears at OQ four CLK cycles after IJKLMNOP is sampled into the
OSERDES. This latency is consistent with the
OSERDES latency of four CLK cycles.
The operation of a 3-State Controller is illustrated in
case shown in a bidirectional system where the IOB must be frequently 3-stated.
X-Ref Target - Figure 8-19
OBUFT.O
CLKDIV
Figure 8-19: OSERDES Data Flow and Latency in 4:1 DDR Mode
CLK
OQ
TQ
D1
D2
D3
D4
T1
T2
T3
T4
www.xilinx.com
1
1
1
1
A
B
C
D
Event 1
Clock
A B C D E F G H
G
E
H
F
0
0
1
0
Table 8-10
Clock
Event 2
E F
Figure
K
J
L
I
listing of a 8:1 DDR mode
H
8-19. The example is a 4:1 DDR
I J K L
1
1
1
1
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_8_19_100307
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