XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 205
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XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
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Table 5-8: Distributed RAM Timing Parameters
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Sequential Delays for a Slice LUT Configured as RAM (Distributed RAM)
Setup and Hold Times for a Slice LUT Configured as RAM (Distributed RAM)
Clock CLK
Notes:
1. This parameters includes a LUT configured as a two-bit distributed RAM.
2. T
3. Parameter includes AI/BI/CI/DI configured as a data input (DI2).
T
T
T
T
T
T
T
ACK
SHCKO
DS
WS
WPH
WPL
WC
XXCK
/T
/T
/T
DH
WH
(1)
CKA
= Setup Time (before clock edge), and T
(3)
Parameter
Distributed RAM Timing Parameters
Table 5-8
of the paths in
shows the timing parameters for the distributed RAM in SLICEM for a majority
AX/BX/CX/DX configured as
data input (DI1)
A/B/C/D address inputs
WE input
CLK to A/B/C/D outputs
Figure
CKXX
Function
5-27.
= Hold Time (after clock edge).
www.xilinx.com
Time after the CLK of a write operation that the
data written to the distributed RAM is stable on
the A/B/C/D output of the slice.
Time before/after the clock that data must be
stable at the AX/BX/CX/DX input of the slice.
Time before/after the clock that address signals
must be stable at the A/B/C/D inputs of the slice
LUT (configured as RAM).
Time before/after the clock that the write enable
signal must be stable at the WE input of the slice
LUT (configured as RAM).
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum clock period to meet address write
cycle time.
(2)
Description
CLB / Slice Timing Models
205
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