XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 265
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XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 265 of 385
- Download datasheet (14Mb)
X-Ref Target - Figure 6-56
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
External Termination
DCI
HSTL_II_DCI_18
HSTL Class II (1.8V)
HSTL_II_18
2R
2R
Figure 6-56: HSTL Class II (1.8V) with Unidirectional Termination
IOB
VRN
VRP
Table 6-22
Table 6-22: Differential HSTL Class I (1.8V) DC Voltage Specifications
Figure 6-56
Class II (1.8V) with unidirectional termination.
Notes:
1. Common mode voltage: V
2. Crossover point: V
V
V
V
V
V
V
V
CCO
TT
IN
DIFF
CM
DIFF
X
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
(Crossover)
(DC)
(DC)
(DC)
(AC)
V
V
TT
lists the differential HSTL Class I (1.8V) DC voltage specifications.
(1)
CCO
shows a sample circuit illustrating a valid termination technique for HSTL
= 0.9V
R P = Z 0 = 50Ω
= 1.8V
(2)
IOB
X
where V
CM
www.xilinx.com
P
= V
– V
Z 0
R P = Z 0 = 50Ω
Z 0
P
N
– ((V
= 0 (AC coupled)
P
Specific Guidelines for I/O Supported Standards
– V
V
TT
N
IOB
V
)/2)
= 0.9V
CCO
–0.30
Min
0.20
0.83
0.40
0.83
1.7
–
2R
2R
= 1.8V
VRP
VRN
IOB
V
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
REF
V
REF
= 0.9V
V
= 0.9V
CCO
Typ
1.8
–
–
–
–
–
HSTL_II_DCI_18
× 0.5
HSTL_II_18
+
–
+
–
ug190_6_53_030306
V
V
V
CCO
CCO
CCO
Max
1.08
1.08
1.9
–
+ 0.30
+ 0.60
+ 0.60
265
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