XC5VSX95T-2FF1136I Xilinx Inc, XC5VSX95T-2FF1136I Datasheet - Page 184
![FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-2FF1136I
Manufacturer Part Number
XC5VSX95T-2FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-2FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VSX95T-2FF1136I
Manufacturer:
XILXIN
Quantity:
20 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 184 of 385
- Download datasheet (14Mb)
Chapter 5: Configurable Logic Blocks (CLBs)
184
X-Ref Target - Figure 5-8
If four single-port 64 x 1-bit modules are built, the four RAM64X1S primitives can occupy
a SLICEM, as long as they share the same clock, write enable, and shared read and write
port address inputs. This configuration equates to 64 x 4-bit single-port distributed RAM.
X-Ref Target - Figure 5-9
If two dual-port 64 x 1-bit modules are built, the two RAM64X1D primitives can occupy a
SLICEM, as long as they share the same clock, write enable, and shared read and write port
address inputs. This configuration equates to 64 x 2-bit dual-port distributed RAM.
DPRA[5:0]
WCLK
A[5:0]
WCLK
A[5:0]
WE
WE
D
D
Figure 5-8: Distributed RAM (RAM64X1S)
Figure 5-9: Distributed RAM (RAM64X1D)
6
(WE/CE)
(D[6:1])
www.xilinx.com
(CLK)
(DX)
(D[6:1])
(WE/CE)
(C[6:1])
(CLK)
6
(DX)
RAM64X1S
DI1
A[6:1]
WA[6:1]
CLK
WE
RAM64X1D
6
6
6
6
SPRAM64
DI1
A[6:1]
WA[6:1]
CLK
WE
DI1
A[6:1]
WA[6:1]
CLK
WE
DPRAM64
DPRAM64
O6
O6
O6
O
SPO
DPO
D Q
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
D Q
D Q
(Optional)
ug190_5_07_032706
Output
Registered
Output
(Optional)
(Optional)
UG190_5_09_050506
Registered
Output
Registered
Output
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