LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 202

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LAN9311-NZW

Manufacturer Part Number
LAN9311-NZW
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LAN9311-NZW

Number Of Primary Switch Ports
2
Internal Memory Buffer Size
32
Operating Supply Voltage (typ)
3.3V
Fiber Support
No
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temperature Classification
Commercial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9311-NZW
Manufacturer:
Standard
Quantity:
2
Part Number:
LAN9311-NZW
Manufacturer:
Microchip Technology
Quantity:
10 000
Revision 1.7 (06-29-10)
14.2.5
14.2.5.1
BITS
31:0
Timestamp High (TS_HI)
This field contains the high 32-bits of the timestamp taken on the receipt of
a 1588 Sync or Delay_Req packet.
IEEE 1588
This section details the IEEE 1588 timestamp related registers. Each port of the LAN9311/LAN9311i
has a 1588 timestamp block with 8 related registers, 4 for transmit capture and 4 for receive capture.
These sets of registers are identical in functionality for each port, and thus their register descriptions
have been consolidated. In these cases, the register names will be amended with a lowercase “x” in
place of the port designation. The wildcard “x” should be replaced with “1”, “2”, or “MII” for the Port 1,
Port 2, and Port 0(Host MAC) respectively. A list of all the 1588 related registers can be seen in
Table
Stamp Unit," on page
Port x 1588 Clock High-DWORD Receive Capture Register (1588_CLOCK_HI_RX_CAPTURE_x)
Note: The selection between Sync or Delay_Req packets is based on the corresponding
Note: There are multiple instantiations of this register, one for each port of the LAN9311/LAN9311i.
Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to
14.1. For more information on the IEEE 1588, refer to
master/slave bit in the
Refer to
the switch fabric.
Offset:
Section 14.2.5
155.
Port 1: 100h
Port 2: 120h
Port 0: 140h
DESCRIPTION
1588 Configuration Register
for additional information.
DATASHEET
202
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Size:
(1588_CONFIG).
Chapter 11, "IEEE 1588 Hardware Time
32 bits
TYPE
SMSC LAN9311/LAN9311i
RO
00000000h
DEFAULT
Datasheet

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